Base Firmware

This commit is contained in:
Alecks 2025-08-01 14:35:49 +08:00
parent 7d28740beb
commit 4ee13ec44b
54 changed files with 18849 additions and 0 deletions

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@ -18,3 +18,8 @@ compile_commands.json
CTestTestfile.cmake
_deps
# ---> Output
*.o
# ---> Folder
/EWARM/WiseEye-LTE/BrowseInfo

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{
"workspace": {
"path": "${workspaceFolder}\\EWARM\\Project.eww"
},
"workspaces": {
"${workspaceFolder}\\EWARM\\Project.eww": {
"configs": {
"${workspaceFolder}\\EWARM\\WiseEye-LTE.ewp": "WiseEye-LTE"
},
"selected": {
"path": "${workspaceFolder}\\EWARM\\WiseEye-LTE.ewp"
}
},
"${workspaceFolder}\\EWARM\\WiseEye_LTE.eww": {
"configs": {
"${workspaceFolder}\\EWARM\\WiseEye-LTE.ewp": "WiseEye-LTE"
},
"selected": {
"path": "${workspaceFolder}\\EWARM\\WiseEye-LTE.ewp"
}
}
},
"workbench": {
"path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.2"
},
"configs": {
"${workspaceFolder}\\EWARM\\WiseEye-LTE.ewp": "WiseEye-LTE"
},
"project": {
"path": "${workspaceFolder}\\EWARM\\WiseEye-LTE.ewp"
}
}

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{
"C_Cpp.default.configurationProvider": "iarsystems.iar-build",
"files.associations": {
"eg91.h": "c",
"lte_comms.h": "c"
}
}

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#ifndef EG91_H
#define EG91_H
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include "eg91_conf.h"
/* Private Constants --------------------------------------------------------*/
#define RET_NONE 0x0000 /* RET_NONE shall be 0x0: don't change this value! */
#define RET_CRLF 0x0001
#define RET_OK 0x0002 /* do not change this value */
#define RET_SIM_READY 0x0004
#define RET_ARROW 0x0008
#define RET_SENT 0x0010 /* do not change this value */
#define RET_OPEN 0x0020
#define RET_ERROR 0x0040 /* do not change this value */
#define RET_URC_CLOSED 0x0080
#define RET_URC_RECV 0x0100
#define RET_URC_IN_FULL 0x0200
#define RET_URC_INCOM 0x0400
#define RET_URC_PDPDEACT 0x0800
#define RET_URC_DNS 0x1000
#define RET_BUF_FULL 0x2000 /* do not change this value */
#define RET_READ 0x4000
#define RET_CME_ERROR 0x8000 /* do not change this value */
#define RET_CMS_ERROR 0x10000
#define RET_POWERED_DOWN 0x20000
#define RET_SEND 0x40000
#define RET_RESP 0x80000
#define RET_NETCLOSE 0x80010
#define RET_UART_READY 0x90000
#define NUM_RESPONSES 23
/* Timeouts modem dependent */
#define EG91_TOUT_SHORT 1000 /* 50 ms 1000 */
#define EG91_TOUT_100 100 /* 100 ms */
#define EG91_TOUT_300 350 /* 0,3 sec + margin */
#define EG91_TOUT_ATSYNC 500
/* Timeouts network dependent */
#define EG91_TOUT_5000 5500 /* 5 sec + margin */
#define EG91_TOUT_15000 16500 /* 15 sec + margin */
#define EG91_TOUT_40000 42000 /* 40 sec + margin */
#define EG91_TOUT_60000 64000 /* 1 min + margin */
#define EG91_TOUT_75000 78000 /* 75 sec + margin */
#define EG91_TOUT_150000 156000 /* 2,5 min + margin */
#define EG91_TOUT_180000 186000 /* 3 min + margin */
/* Exported constants---------------------------------------------------------*/
#define EG91_MAX_APN_NAME_SIZE 32
#define EG91_MAX_USER_NAME_SIZE 32
#define EG91_MAX_PSW_NAME_SIZE 32
#define EG91_ERROR_STRING_SIZE 40
#define EG91_MFC_SIZE 10
#define EG91_PROD_ID_SIZE 50
#define EG91_FW_REV_SIZE 100
#define EG91_IMEI_SIZE 50
#define EG91_ICCID_SIZE 50
#define EG91_IMSI_SIZE 50
/* Exported macro-------------------------------------------------------------*/
#ifdef MIN
#undef MIN
#endif
#define MIN(a, b) ((a) < (b) ? (a) : (b))
/* Exported typedef ----------------------------------------------------------*/
typedef int8_t (*IO_Init_Func)(void);
typedef int8_t (*IO_DeInit_Func)(void);
typedef int8_t (*IO_Baudrate_Func)(uint32_t BaudRate);
typedef void (*IO_Flush_Func)(void);
typedef int16_t (*IO_Send_Func)(uint8_t*, uint16_t);
typedef int16_t (*IO_ReceiveOne_Func)(uint8_t *pSingleData);
typedef uint32_t (*App_GetTickCb_Func)(void);
typedef struct
{
uint32_t retVal;
char retStr[100];
} EG91_RetKeywords_t;
typedef enum
{
EG91_RETURN_OK = RET_OK, /* shall be aligned with above definitions */
EG91_RETURN_ERROR = RET_ERROR, /* shall be aligned with above definitions */
EG91_RETURN_CME_ERROR = RET_CME_ERROR, /* shall be aligned with above definitions */
EG91_RETURN_RETRIEVE_ERROR = -1,
EG91_RETURN_SEND_ERROR = -2
} EG91_Return_t;
typedef enum
{
/* See CME Error Codes */
EG91_SIM_ERROR = 0,
EG91_SIM_NOT_INSERTED = 10,
EG91_SIM_PIN_REQUIRED = 11,
EG91_SIM_PUK_REQUIRED = 12,
EG91_SIM_FAILURE = 13,
EG91_SIM_BUSY = 14,
EG91_SIM_WRONG = 15,
EG91_INCORRECT_PSW = 16,
EG91_SIM_PIN2_REQUIRED = 17,
EG91_SIM_PUK2_REQUIRED = 18,
EG91_OPERATION_NOT_ALLOW = 3,
EG91_SIM_READY = 0xFF
} EG91_SIMState_t;
typedef enum
{
EG91_NRS_NOT_REGISTERED = 0x00,
EG91_NRS_HOME_NETWORK = 0x01,
EG91_NRS_TRYING = 0x02,
EG91_NRS_REG_DENIED = 0x03,
EG91_NRS_UNKNOWN = 0x04,
EG91_NRS_ROAMING = 0x05,
EG91_NRS_ERROR = 0xFF
} EG91_NetworkRegistrationState_t;
typedef enum
{
EG91_AP_NOT_CONFIG = 0x00,
EG91_AP_CONFIGURED = 0x01,
EG91_AP_ACVTIVATED = 0x02,
EG91_AP_ERROR = 0xFF
} EG91_APState_t;
typedef enum
{
EG91_INIT_RET_OK = RET_OK, /*shall be aligned with above definitions */
EG91_INIT_RET_AT_ERR = 0x04,
EG91_INIT_RET_SIM_ERR = 0x08,
EG91_INIT_RET_IO_ERR = 0x10,
EG91_INIT_OTHER_ERR = 0x20
} EG91_InitRet_t;
typedef enum
{
EG91_SEND_RET_UART_FAIL = 0x1,
EG91_SEND_RET_SENT = RET_SENT, /*shall be aligned with above definitions */
EG91_SEND_RET_BUF_FULL = RET_BUF_FULL, /*shall be aligned with above definitions */
EG91_SEND_RET_CONN_ERR = RET_ERROR /*shall be aligned with above definitions */
} EG91_SendRet_t;
typedef enum
{
EG91_RECEIVE_RET_INCOMPLETE = 0x01,
EG91_RECEIVE_RET_OK = RET_OK, /*shall be aligned with above definitions */
EG91_RECEIVE_RET_PARAM_ERR = 0x04,
EG91_RECEIVE_RET_COM_ERR = 0x08
} EG91_ReceiveRet_t;
typedef enum
{
EG91_TCP_CONNECTION = 0,
EG91_UDP_CONNECTION = 1,
EG91_TCP_LISTENER_CONNECTION = 2,
EG91_UDP_SERVER_CONNECTION = 3
} EG91_ConnType_t;
typedef enum
{
EG91_BUFFER_MODE = 0,
EG91_DIRECT_PUSH = 1,
EG91_TRANSPARENT_MODE = 2
} EG91_AccessMode_t;
/**
* \brief Authentication settings for C2C network
*/
typedef enum
{
EG91_AUTHENT_NONE = 0x00,
EG91_AUTHENT_PAP = 0x01,
EG91_AUTHENT_CHAP = 0x02,
EG91_AUTHENT_PAP_CHAP = 0x03
} EG91_Authent_t;
typedef enum
{
EG91_UART_FLW_CTL_NONE = 0x00,
EG91_UART_FLW_CTL_RTS = 0x01,
EG91_UART_FLW_CTL_CTS = 0x02,
EG91_UART_FLW_CTL_RTS_CTS = 0x03,
} EG91_UART_FLW_CTL_t;
typedef struct
{
uint32_t BaudRate;
uint32_t FlowControl;
} EG91_UARTConfig_t;
typedef struct
{
uint8_t ContextID; /*!< range is 1-20 */
uint8_t ContextType; /*!< shall be 1 (IpV */
uint8_t ApnString[32]; /*!< access point name, string of chars */
uint8_t Username[32]; /*!< user name, string of chars */
uint8_t Password[32]; /*!< password, string of chars */
EG91_Authent_t Authentication;
} EG91_APConfig_t;
typedef struct
{
EG91_ConnType_t Type;
EG91_AccessMode_t AccessMode;
uint8_t ConnectID;
uint16_t RemotePort;
uint16_t LocalPort;
char *Url;
} EG91_Conn_t;
typedef struct
{
EG91_ConnType_t Type;
EG91_AccessMode_t AccessMode;
uint16_t ComulatedQirdData;
uint16_t HaveReadLength;
uint16_t UnreadLength;
int16_t UartRemaining; /* if Timeout respects UART speed this should always be 0 */
} EG91_Socket_t;
typedef struct
{
IO_Init_Func IO_Init;
IO_DeInit_Func IO_DeInit;
IO_Baudrate_Func IO_Baudrate;
IO_Flush_Func IO_FlushBuffer;
IO_Send_Func IO_Send;
IO_ReceiveOne_Func IO_ReceiveOne;
} EG91_IO_t;
typedef struct
{
EG91_SIMState_t SimStatus;
uint8_t RegistStatusString[3];
uint8_t IMSI[EG91_IMSI_SIZE];
uint8_t ICCID[EG91_ICCID_SIZE + 1];
} EG91_SIMInfo_t;
typedef struct
{
uint8_t Manufacturer[EG91_MFC_SIZE];
uint8_t ProductID[EG91_PROD_ID_SIZE];
uint8_t FW_Rev[EG91_FW_REV_SIZE];
uint8_t Imei[EG91_IMEI_SIZE]; /*International Mobile Equipment Identity*/
EG91_SIMInfo_t SimInfo;
uint8_t APsActive;
uint8_t APContextState[EG91_MAX_CONTEXTS]; /* to decide if keeping all EG91_APConfig_t info. maybe at c2c SW level*/
EG91_Socket_t SocketInfo[EG91_MAX_SOCKETS]; /* to decide if keeping all EG91_Conn_t info. maybe at c2c SW level*/
EG91_UARTConfig_t UART_Config;
EG91_IO_t fops;
App_GetTickCb_Func GetTickCb;
uint8_t CmdResp[EG91_CMD_SIZE];
uint32_t RemainRxData;
} EG91Object_t;
/* Exported functions --------------------------------------------------------*/
/* ==== Init and status ==== */
EG91_Return_t EG91_RegisterBusIO(EG91Object_t *Obj, IO_Init_Func IO_Init,
IO_DeInit_Func IO_DeInit, IO_Baudrate_Func IO_Baudrate,
IO_Send_Func IO_Send, IO_ReceiveOne_Func IO_ReceiveOne,
IO_Flush_Func IO_Flush);
EG91_InitRet_t EG91_Init(EG91Object_t *Obj);
EG91_Return_t EG91_PowerDown(EG91Object_t *Obj);
/* ==== Registration and network selection ==== */
EG91_Return_t EG91_GetSignalQualityStatus(EG91Object_t *Obj, int32_t *Qvalue);
EG91_Return_t EG91_PSAttach(EG91Object_t *Obj);
EG91_Return_t EG91_AutomaticPlmnSelection(EG91Object_t *Obj);
EG91_Return_t EG91_SetFullFunctionality(EG91Object_t *Obj);
EG91_Return_t EG91_SetGSMLTE(EG91Object_t *Obj);
EG91_NetworkRegistrationState_t EG91_GetCsNetworkRegistrationStatus(EG91Object_t *Obj);
EG91_NetworkRegistrationState_t EG91_GetPsNetworkRegistrationStatus(EG91Object_t *Obj);
EG91_Return_t EG91_ListOperators(EG91Object_t *Obj, char *Operators);
EG91_Return_t EG91_GetCurrentOperator(EG91Object_t *Obj, char *Operator, uint8_t Bufsize);
EG91_Return_t EG91_ForceOperator(EG91Object_t *Obj, int32_t OperatorCode);
/* ==== AP Connection ==== */
EG91_Return_t EG91_ConfigureAP(EG91Object_t *Obj, EG91_APConfig_t *ApConfig);
EG91_Return_t EG91_Activate(EG91Object_t *Obj, uint8_t ContextID);
EG91_Return_t EG91_Deactivate(EG91Object_t *Obj, uint8_t ContextID);
EG91_APState_t EG91_IsActivated(EG91Object_t *Obj, uint8_t ContextID);
/* ====IP Addr ==== */
EG91_Return_t EG91_GetActiveIpAddresses(EG91Object_t *Obj, char *IPaddr_string, uint8_t *IPaddr_int);
/* ==== Ping ==== */
#if (EG91_USE_PING == 1)
EG91_Return_t EG91_Ping(EG91Object_t *Obj, uint8_t ContextID, char *host_addr_string, uint16_t count, uint16_t rep_delay_sec);
#endif
/* ==== Client connection ==== */
EG91_Return_t EG91_DNS_LookUp(EG91Object_t *Obj, uint8_t ContextID, const char *IPaddr_string, uint8_t *IPaddr_int);
EG91_Return_t EG91_OpenClientConnection(EG91Object_t *Obj, uint8_t ContextID, EG91_Conn_t *conn);
EG91_Return_t EG91_CloseClientConnection(EG91Object_t *Obj, EG91_Conn_t *conn);
EG91_SendRet_t EG91_SendData(EG91Object_t *Obj, uint8_t Socket, uint8_t *pdata, uint16_t Reqlen, uint16_t *SentLen, uint32_t Timeout);
EG91_ReceiveRet_t EG91_ReceiveData(EG91Object_t *Obj, uint8_t Socket, uint8_t *pdata, uint16_t Reqlen, uint16_t *Receivedlen, uint32_t Timeout);
/* ==== Miscellaneus ==== */
EG91_Return_t EG91_ResetToFactoryDefault(EG91Object_t *Obj);
EG91_Return_t EG91_SetUARTBaudrate(EG91Object_t *Obj, EG91_UARTConfig_t *pconf);
EG91_Return_t EG91_GetUARTConfig(EG91Object_t *Obj, EG91_UARTConfig_t *pconf);
void EG91_GetManufacturer(EG91Object_t *Obj, uint8_t *Manufacturer);
void EG91_GetProductID(EG91Object_t *Obj, uint8_t *ProductID);
void EG91_GetFWRevID(EG91Object_t *Obj, uint8_t *Fw_ver);
EG91_Return_t EG91_RetrieveLastErrorDetails(EG91Object_t *Obj, char *error_string);
/* Application must provide callback function that gives a Timer Tick in ms (e.g. HAL_GetTick())*/
EG91_Return_t EG91_RegisterTickCb(EG91Object_t *Obj, App_GetTickCb_Func GetTickCb);
#ifdef __cplusplus
}
#endif
#endif // EG91_H

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/**
******************************************************************************
* @file EG91_conf.h
* @author MCD Application Team
* @brief EG91 configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted, provided that the following conditions are met:
*
* 1. Redistribution of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EG91_CONF_H
#define __EG91_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* --------------------------------------------------------------------------- */
/* EG91 static parameter that can be configured by the user before compilation */
/* --------------------------------------------------------------------------- */
/* Max sockets allowed by modem is 12 but beter use max 9 (sw not tested above) */
#define EG91_MAX_SOCKETS 1
/* Max context allowed by modem is 20 but beter use max 9 (sw not tested above) */
#define EG91_MAX_CONTEXTS 1
/* 256 is normally sufficient, but if some params like URL are very long string it can be increased*/
#define EG91_CMD_SIZE 256
/* EG91 and STM32 shall have same baudrate to communicate */
#define EG91_DEFAULT_BAUDRATE 115200
/* Rx and Tx buffer size, depend as the applic handles the buffer */
#define EG91_TX_DATABUF_SIZE 1460 /* mbedTLS needs at least 1460 */
#define EG91_RX_DATABUF_SIZE 1500
/* 0 to disable, 1 to enable PING feature */
#define EG91_USE_PING 1
#ifdef __cplusplus
}
#endif
#endif /* __EG91_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file gpio.h
* @brief This file contains all the function prototypes for
* the gpio.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_GPIO_Init(void);
/* USER CODE BEGIN Prototypes */
void LEDStatus_Active(void);
void LEDStatus_Inactive(void);
void LTE_HardwarePowerUp(void);
void LTE_HardwarePowerDown(void);
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ GPIO_H__ */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file icache.h
* @brief This file contains all the function prototypes for
* the icache.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __ICACHE_H__
#define __ICACHE_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_ICACHE_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __ICACHE_H__ */

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#ifndef __LTE_COMMS_H_
#define __LTE_COMMS_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "eg91.h"
#include "eg91_conf.h"
#define LTE_COMMS_MAX_DELAY 0xFFFFU
#define LTE_OPERATOR_STRING 30
#define LTE_OPERATORS_LIST 6 * LTE_OPERATOR_STRING
#define LTE_IPADDR_STRING 35
#define LTE_IPADDR_LIST 3 * LTE_IPADDR_STRING
#define LTE_ERROR_STRING 40
#define LTE_MAN_SIZE 16
#define LTE_PROD_ID_SIZE 16
#define LTE_FW_REV_SIZE 100
#define LTE_IMEI_SIZE 16
#define LTE_ICCID_SIZE 20
#define LTE_MAX_NOS 100 /* Network Operators */
#define LTE_MAX_CONNECTION EG91_MAX_SOCKETS
#define LTE_PAYLOAD_SIZE 1500 /* Should be = or > than EG91_RX_DATABUF_SIZE */
typedef enum
{
LTE_IPV4 = 0x01,
LTE_IPV6 = 0x02
} LTE_IPVer_t;
typedef enum
{
LTE_AUTHENT_NONE = 0x00,
LTE_AUTHENT_PAP = 0x01,
LTE_AUTHENT_CHAP = 0x02,
LTE_AUTHENT_PAP_CHAP = 0x03
} LTE_Authent_t;
typedef enum
{
LTE_TCP_PROTOCOL = 0,
LTE_UDP_PROTOCOL = 1,
LTE_TCP_LISTENER_PROTOCOL = 2,
LTE_UDP_SERVICE_PROTOCOL = 3
} LTE_Protocol_t;
typedef enum
{
/* Registration Status */
LTE_REGISTATUS_NOT_REGISTERED = 0x00,
LTE_REGISTATUS_HOME_NETWORK = 0x01,
LTE_REGISTATUS_TRYING = 0x02,
LTE_REGISTATUS_REG_DENIED = 0x03,
LTE_REGISTATUS_UNKNOWN = 0x04,
LTE_REGISTATUS_ROAMING = 0x05,
LTE_REGISTATUS_SIM_NOT_INSERTED = 0x0A,
LTE_REGISTATUS_SIM_PIN_REQUIRED = 0x0B,
LTE_REGISTATUS_SIM_PUK_REGUIRED = 0x0C,
LTE_REGISTATUS_SIM_FAILURE = 0x0D,
LTE_REGISTATUS_SIM_BUSY = 0x0E,
LTE_REGISTATUS_SIM_WRONG = 0x0F,
LTE_REGISTATUS_INCORRECT_PSW = 0x10,
LTE_REGISTATUS_SIM_PIN2_REQUIRED = 0x11,
LTE_REGISTATUS_SIM_PUK2_REQUIRED = 0x12,
LTE_REGISTATUS_OP_NOT_ALLOWED = 0x13,
LTE_REGISTATUS_ERROR = 0xFF
} LTE_Registatus_t;
typedef enum
{
LTE_AP_NOT_CONFIG = 0x00,
LTE_AP_CONFIGURED = 0x01,
LTE_AP_ACTIVATED = 0x02,
LTE_AP_ERROR = 0xFF
} LTE_APState_t;
typedef enum
{
LTE_RET_OK = 0x00,
LTE_RET_NOT_SUPPORTED = 0x01,
LTE_RET_ERROR = 0x02
} LTE_Ret_t;
typedef enum
{
LTE_SEND_OK = 0x00,
LTE_SEND_BUF_FULL = 0x01,
LTE_SEND_ERROR = 0xFF
} LTE_SendStatus_t;
int Network_Init(void);
void LTE_ConvertIpAddrToString(const uint8_t * ipArray, char *returnStr);
LTE_Registatus_t LTE_Init(uint16_t registration_timeout_sec);
LTE_Ret_t LTE_GetSignalQualityStatus(int32_t *qValue);
LTE_Ret_t LTE_ListOperators(char *operator);
LTE_Ret_t LTE_GetCurrentOperator (char *operator, int32_t bufSize);
LTE_Ret_t LTE_ForceOperator(int32_t code);
LTE_Ret_t LTE_ConfigureAP(uint8_t contextType, const char *apn, const char *username,
const char *password, uint8_t authenticationMode);
LTE_Ret_t LTE_Connect(void);
LTE_Ret_t LTE_Disconnect(void);
LTE_APState_t LTE_isConnected(void);
LTE_Ret_t LTE_GetActiveIpAddress(char * ipAddrStr, uint8_t *ipAddrInt);
LTE_Ret_t LTE_Ping(char *address, uint16_t count, uint16_t timeout);
LTE_Ret_t LTE_GetHostAddress(const char *address, uint8_t *ipaddr);
LTE_Ret_t LTE_StartClientConnection(uint32_t socket, LTE_Protocol_t type, const char *url,
uint8_t *ipaddr, uint16_t port, uint16_t local_port);
LTE_Ret_t LTE_StopClientConnection(uint32_t socket);
LTE_Ret_t LTE_StartServerConnection(uint32_t socket, LTE_Protocol_t type, uint16_t port, uint16_t local_port);
LTE_Ret_t LTE_StopServerConnection(uint32_t socket);
LTE_SendStatus_t LTE_SendData(uint32_t socket, uint8_t *pdata, uint16_t reqLen, uint16_t *sentDataLen, uint32_t timeout);
LTE_Ret_t LTE_ReceiveData(uint32_t socket, uint8_t *pdata, uint16_t reqLen, uint16_t *rcvDataLen, uint32_t timeout);
LTE_Ret_t LTE_RetrieveLastErrorDetails(char *errorStr);
LTE_Ret_t LTE_PowerOff(void);
LTE_Ret_t LTE_GetModuleFirmwareRevision(char *rev);
LTE_Ret_t LTE_GetModuleID(char *productId);
LTE_Ret_t LTE_GetModuleName(char *moduleName);
LTE_Ret_t LTE_GetSimId(char *simId);
LTE_Ret_t LTE_GetIMEI(char *imei);
#ifdef __cplusplus
}
#endif
#endif /* __LTE_COMMS_H_ */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32wbaxx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
#undef MIN
#define MIN(a,b) ( ((a)<(b)) ? (a) : (b) )
#define MAX(a,b) ( ((a)<(b)) ? (b) : (a) )
#define ROUND_DOWN(a,b) ( ((a) / (b)) * (b) )
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define LTE_TX_Pin GPIO_PIN_12
#define LTE_TX_GPIO_Port GPIOB
#define DEBUG_TX_Pin GPIO_PIN_11
#define DEBUG_TX_GPIO_Port GPIOB
#define LTE_RX_Pin GPIO_PIN_8
#define LTE_RX_GPIO_Port GPIOA
#define STATUS_LED_Pin GPIO_PIN_7
#define STATUS_LED_GPIO_Port GPIOB
#define LTE_EN_Pin GPIO_PIN_4
#define LTE_EN_GPIO_Port GPIOB
#define LTE_RST_Pin GPIO_PIN_0
#define LTE_RST_GPIO_Port GPIOB
#define LTE_PWRKEY_Pin GPIO_PIN_15
#define LTE_PWRKEY_GPIO_Port GPIOB
#define DEBUG_RX_Pin GPIO_PIN_10
#define DEBUG_RX_GPIO_Port GPIOA
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file rtc.h
* @brief This file contains all the function prototypes for
* the rtc.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RTC_H__
#define __RTC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern RTC_HandleTypeDef hrtc;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_RTC_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __RTC_H__ */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32wbaxx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32WBAxx_HAL_CONF_H
#define STM32WBAxx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_GTZC_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
#define HAL_HSEM_MODULE_ENABLED
/*#define HAL_I2C_MODULE_ENABLED */
#define HAL_ICACHE_MODULE_ENABLED
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_PKA_MODULE_ENABLED */
/*#define HAL_RAMCFG_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/*#define HAL_SAI_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_TSC_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_EXTI_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 32000000UL /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations in voltage
and temperature.*/
#if defined (RCC_LSI2_SUPPORT)
#if !defined (LSI2_VALUE)
#define LSI2_VALUE 32000UL /*!< LSI2 Typical Value in Hz*/
#endif /* LSI2_VALUE */
#endif
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for SAI1 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U /*!< Enable prefetch */
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## Register callback feature configuration ############### */
/**
* @brief Set below the peripheral configuration to "1U" to add the support
* of HAL callback registration/unregistration feature for the HAL
* driver(s). This allows user application to provide specific callback
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
* the default weak callback functions (see each stm32wbaxx_hal_ppp.h file
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
* for each PPP peripheral).
*/
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */
#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* ################## CRYP peripheral configuration ########################## */
#define USE_HAL_CRYP_SUSPEND_RESUME 0U
/* ################## HASH peripheral configuration ########################## */
#define USE_HAL_HASH_SUSPEND_RESUME 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32wbaxx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32wbaxx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32wbaxx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32wbaxx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32wbaxx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32wbaxx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32wbaxx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32wbaxx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32wbaxx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_GTZC_MODULE_ENABLED
#include "stm32wbaxx_hal_gtzc.h"
#endif /* HAL_GTZC_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32wbaxx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_HSEM_MODULE_ENABLED
#include "stm32wbaxx_hal_hsem.h"
#endif /* HAL_HSEM_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32wbaxx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_ICACHE_MODULE_ENABLED
#include "stm32wbaxx_hal_icache.h"
#endif /* HAL_ICACHE_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32wbaxx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32wbaxx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32wbaxx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_PKA_MODULE_ENABLED
#include "stm32wbaxx_hal_pka.h"
#endif /* HAL_PKA_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32wbaxx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RAMCFG_MODULE_ENABLED
#include "stm32wbaxx_hal_ramcfg.h"
#endif /* HAL_RAMCFG_MODULE_ENABLED */
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32wbaxx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32wbaxx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32wbaxx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32wbaxx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32wbaxx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32wbaxx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32wbaxx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32wbaxx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32wbaxx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32wbaxx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32wbaxx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32wbaxx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32WBAxx_HAL_CONF_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32wbaxx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32WBAxx_IT_H
#define __STM32WBAxx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void USART1_IRQHandler(void);
void HSEM_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32WBAxx_IT_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file usart.h
* @brief This file contains all the function prototypes for
* the usart.c file
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USART_H__
#define __USART_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
#include <stdio.h>
#include <yfuns.h>
#include <string.h>
/* USER CODE END Includes */
extern UART_HandleTypeDef hlpuart1;
extern UART_HandleTypeDef huart1;
/* USER CODE BEGIN Private defines */
// #define LOG_APP_DEBUG
#define LOG_APP_ERROR
#define LOG_APP_LOG
#define LOG_APP_LTE
/**
* @brief Application general debug messages
*
* Enable by defining `LOG_APP_DEBUG` in config.h.
*/
#ifdef LOG_APP_DEBUG
# define APP_DEBUG_MSG(a, ...) printf(("DEBUG: " a), ##__VA_ARGS__)
#else
# define APP_DEBUG_MSG(...) ((void)0)
#endif
/**
* @brief Application error messages
*
* Enable by defining `LOG_APP_ERROR` in config.h.
*/
#ifdef LOG_APP_ERROR
# define APP_ERROR_MSG(a, ...) printf(("ERROR: "a), ##__VA_ARGS__)
#else
# define APP_ERROR_MSG(...) ((void)0)
#endif
/**
* @brief Application logging messages
*
* Enable by defining `LOG_APP_LOG` in config.h.
*/
#ifdef LOG_APP_LOG
# define APP_LOG_MSG(a, ...) printf((a), ##__VA_ARGS__)
#else
# define APP_LOG_MSG(...) ((void)0)
#endif
/**
* @brief Application logging lte messages
*
* Enable by defining `LOG_APP_LTE` in config.h.
*/
#ifdef LOG_APP_LTE
# define APP_LTE_MSG(a, ...) printf(("AT RSP:" a), ##__VA_ARGS__)
#else
# define APP_LTE_MSG(...) ((void)0)
#endif
/* USER CODE END Private defines */
void MX_LPUART1_UART_Init(void);
void MX_USART1_UART_Init(void);
/* USER CODE BEGIN Prototypes */
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle);
void LTE_ATSendCommand(const char *cmd);
void LTE_SendATCommand_Test(void);
int8_t LTE_UART_SetBaudrate(uint32_t baudrate);
void LTE_UART_FlushBuffer(void);
int16_t LTE_UART_SendData(uint8_t *pData, uint16_t length);
int16_t LTE_UART_ReceiveSingleData(uint8_t *pSingleData);
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __USART_H__ */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file gpio.c
* @brief This file provides code for the configuration
* of all used GPIO pins.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "gpio.h"
/* USER CODE BEGIN 0 */
#include "usart.h"
/* USER CODE END 0 */
/*----------------------------------------------------------------------------*/
/* Configure GPIO */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/** Configure pins
PC15-OSC32_OUT ------> RCC_OSC32_OUT
PC14-OSC32_IN ------> RCC_OSC32_IN
PA14 (JTCK/SWCLK) ------> DEBUG_JTCK-SWCLK
PA13 (JTMS/SWDIO) ------> DEBUG_JTMS-SWDIO
OSC_OUT ------> RCC_OSC_OUT
OSC_IN ------> RCC_OSC_IN
*/
void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, STATUS_LED_Pin|LTE_EN_Pin|LTE_RST_Pin|LTE_PWRKEY_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : STATUS_LED_Pin LTE_EN_Pin LTE_RST_Pin LTE_PWRKEY_Pin */
GPIO_InitStruct.Pin = STATUS_LED_Pin|LTE_EN_Pin|LTE_RST_Pin|LTE_PWRKEY_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
}
/* USER CODE BEGIN 2 */
void LEDStatus_Active(void)
{
HAL_GPIO_WritePin(STATUS_LED_GPIO_Port, STATUS_LED_Pin, GPIO_PIN_SET);
}
void LEDStatus_Inactive(void)
{
HAL_GPIO_WritePin(STATUS_LED_GPIO_Port, STATUS_LED_Pin, GPIO_PIN_RESET);
}
/**
* @brief Powers up the LTE module (Quectel EG91) using GPIO toggling.
*
* This function simulates pressing the PWRKEY and enables the level translator.
* A wait period is included to allow UART stabilization.
*/
void LTE_HardwarePowerUp(void)
{
HAL_GPIO_WritePin(LTE_EN_GPIO_Port, LTE_EN_Pin, GPIO_PIN_SET);
APP_LOG_MSG(" --- QUECTEL EG91 Power Up ---\r\n");
/* Power up the LTE Module Using Power Key */
HAL_GPIO_WritePin(LTE_PWRKEY_GPIO_Port, LTE_PWRKEY_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(LTE_RST_GPIO_Port, LTE_RST_Pin, GPIO_PIN_RESET);
HAL_Delay(100);
HAL_GPIO_WritePin(LTE_RST_GPIO_Port, LTE_RST_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(LTE_PWRKEY_GPIO_Port, LTE_PWRKEY_Pin, GPIO_PIN_SET);
HAL_Delay(200);
HAL_GPIO_WritePin(LTE_RST_GPIO_Port, LTE_RST_Pin, GPIO_PIN_RESET);
HAL_Delay(350);
HAL_GPIO_WritePin(LTE_PWRKEY_GPIO_Port, LTE_PWRKEY_Pin, GPIO_PIN_RESET);
HAL_Delay(100);
for (uint8_t wait = 0; wait < 12; wait++) {
LEDStatus_Active();
HAL_Delay(500);
LEDStatus_Inactive();
HAL_Delay(500);
// APP_LOG_MSG(".");
}
// APP_LOG_MSG(" Done\r\n");
}
/**
* @brief Powers down the LTE module (Quectel EG91) via GPIO toggling.
*
* This simulates a long-press of the PWRKEY, then waits 30 seconds to allow the module to shut down safely.
*/
void LTE_HardwarePowerDown(void)
{
APP_LOG_MSG(" --- QUECTEL EG91 Shut Down --- \r\n");
HAL_GPIO_WritePin(LTE_PWRKEY_GPIO_Port, LTE_PWRKEY_Pin, GPIO_PIN_RESET);
HAL_Delay(100);
HAL_GPIO_WritePin(LTE_PWRKEY_GPIO_Port, LTE_PWRKEY_Pin, GPIO_PIN_SET);
HAL_Delay(700);
HAL_GPIO_WritePin(LTE_PWRKEY_GPIO_Port, LTE_PWRKEY_Pin, GPIO_PIN_RESET);
LEDStatus_Active();
// APP_LOG_MSG("Shutting off ");
for (uint8_t wait = 0; wait < 30; wait++)
{
// APP_LOG_MSG(".");
HAL_Delay(1000);
}
// APP_LOG_MSG(" Done\r\n");
LEDStatus_Inactive();
}
/* USER CODE END 2 */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file icache.c
* @brief This file provides code for the configuration
* of the ICACHE instances.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "icache.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* ICACHE init function */
void MX_ICACHE_Init(void)
{
/* USER CODE BEGIN ICACHE_Init 0 */
/* USER CODE END ICACHE_Init 0 */
/* USER CODE BEGIN ICACHE_Init 1 */
/* USER CODE END ICACHE_Init 1 */
/** Enable instruction cache in 1-way (direct mapped cache)
*/
if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK)
{
Error_Handler();
}
if (HAL_ICACHE_Enable() != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ICACHE_Init 2 */
/* USER CODE END ICACHE_Init 2 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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#include <stdlib.h>
#include <stdbool.h>
#include "main.h"
#include "usart.h"
#include "gpio.h"
#include "eg91.h"
#include "lte_comms.h"
#define LTE_CONTEXT_1 1
EG91Object_t Eg91Obj;
static uint16_t rnglocalport = 0;
int Network_Init(void)
{
LTE_Ret_t ret = LTE_RET_ERROR;
LTE_Registatus_t reg_status = LTE_REGISTATUS_UNKNOWN;
int32_t quality_level = 0;
int8_t quality_level_db = 0;
int try_counter = 0;
char moduleInfo[MAX(MAX(MAX(MAX(LTE_FW_REV_SIZE, LTE_MAN_SIZE), LTE_PROD_ID_SIZE), LTE_IMEI_SIZE), LTE_ICCID_SIZE) + 1];
while (ret != LTE_RET_OK)
{
if (try_counter >= 3)
{
ret = LTE_RET_ERROR;
break;
}
else
{
try_counter++;
HAL_Delay(50);
LTE_HardwarePowerUp();
reg_status = LTE_Init(120);
LTE_GetModuleName(moduleInfo);
APP_LOG_MSG("Module Name: %s\r\n", moduleInfo);
memset(moduleInfo, 0, sizeof(moduleInfo));
LTE_GetModuleID(moduleInfo);
APP_LOG_MSG("Product ID: %s\r\n", moduleInfo);
memset(moduleInfo, 0, sizeof(moduleInfo));
LTE_GetModuleFirmwareRevision(moduleInfo);
APP_LOG_MSG("FW Version: %s\r\n", moduleInfo);
memset(moduleInfo, 0, sizeof(moduleInfo));
LTE_GetIMEI(moduleInfo);
APP_LOG_MSG("IMEI: %s\r\n", moduleInfo);
memset(moduleInfo, 0, sizeof(moduleInfo));
LTE_GetSimId(moduleInfo);
APP_LOG_MSG("ICCID: %s\r\n", moduleInfo);
memset(moduleInfo, 0, sizeof(moduleInfo));
if ((reg_status != LTE_REGISTATUS_ERROR) && (reg_status != LTE_REGISTATUS_SIM_NOT_INSERTED) && (reg_status == LTE_REGISTATUS_NOT_REGISTERED))
{
APP_LOG_MSG("Successful Initialization of the Module\r\n\r\n");
memset(moduleInfo, 0, sizeof(moduleInfo));
/* Retrieve the Quality Level of the Connection */
LTE_GetSignalQualityStatus(&quality_level);
if (quality_level != 99)
{
quality_level_db = (int8_t)(-113 + 2 * quality_level);
APP_LOG_MSG("Signal Quality Level %d dBm (GSM Format: %ld)\r\n", quality_level_db, quality_level);
}
else
{
APP_LOG_MSG("Signal Quality Level not detectable\r\n");
}
APP_LOG_MSG("\r\n");
}
switch (reg_status)
{
case LTE_REGISTATUS_HOME_NETWORK:
case LTE_REGISTATUS_ROAMING:
case LTE_REGISTATUS_UNKNOWN:
{
HAL_Delay(1000);
ret = LTE_RET_OK;
APP_LOG_MSG("\r\n >>> Module Registration Successful\r\n\r\n");
break;
}
case LTE_REGISTATUS_TRYING:
{
APP_LOG_MSG("\r\n >>> Module Registration Trying\r\n\r\n");
break;
}
case LTE_REGISTATUS_REG_DENIED:
{
APP_LOG_MSG("\r\n >>> Module Registration Denied\r\n\r\n");
break;
}
case LTE_REGISTATUS_NOT_REGISTERED:
{
APP_LOG_MSG("\r\n >>> Module Registration Failed\r\n\r\n");
break;
}
case LTE_REGISTATUS_ERROR:
{
APP_LOG_MSG("\r\n >>> Module AT Communication Error with the Device\r\n");
APP_LOG_MSG(" >>> Device might be disconnected or wrongly connected\r\n\r\n");
break;
}
case LTE_REGISTATUS_SIM_NOT_INSERTED:
{
APP_LOG_MSG("\r\n >>> SIM is not INSERTED\r\n\r\n");
break;
}
default:
{
APP_LOG_MSG("\r\n >>> Module SIM Error: %d\r\n", reg_status);
APP_LOG_MSG(" >>> Please check if the SIM is inserted and valid, if credentials are ok, etc.\r\n\r\n");
break;
}
}
}
}
return (ret == LTE_RET_OK) ? 0 : -1;
}
void LTE_ConvertIpAddrToString(const uint8_t * ipArray, char *returnStr)
{
snprintf((char*) returnStr, 16, "%d.%d.%d.%d", ipArray[0], ipArray[1], ipArray[2], ipArray[3]);
}
LTE_Registatus_t LTE_Init(uint16_t registration_timeout_sec)
{
EG91_InitRet_t init_status;
EG91_SIMState_t sim_tmp;
LTE_Registatus_t ret = LTE_REGISTATUS_ERROR;
bool signalMsg = false;
/* Channel Signal Quality */
int32_t quality_level = 0;
int8_t quality_level_db = 0;
/* Counter for PS Attachement */
int8_t attRetry = 0;
/* Init for timeout management */
uint32_t tickstart;
uint32_t tickcurrent;
uint32_t registration_timeout_msec = registration_timeout_sec * 1000;
tickstart = HAL_GetTick();
EG91_RegisterTickCb(&Eg91Obj, HAL_GetTick);
if (EG91_RegisterBusIO(&Eg91Obj, (IO_Init_Func)MX_USART1_UART_Init,
(IO_DeInit_Func)HAL_UART_DeInit, (IO_Baudrate_Func)LTE_UART_SetBaudrate,
(IO_Send_Func)LTE_UART_SendData, (IO_ReceiveOne_Func)LTE_UART_ReceiveSingleData,
(IO_Flush_Func)LTE_UART_FlushBuffer) == EG91_RETURN_OK)
{
init_status = EG91_Init(&Eg91Obj);
if (init_status == EG91_INIT_RET_OK)
{
tickcurrent = HAL_GetTick() - tickstart;
while ((tickcurrent < registration_timeout_msec) || (registration_timeout_sec == LTE_COMMS_MAX_DELAY))
{
/* Check Signal Quality*/
if (EG91_GetSignalQualityStatus(&Eg91Obj, &quality_level) == EG91_RETURN_OK)
{
if (quality_level == 99)
{
if (signalMsg == false)
{
APP_LOG_MSG("Signal is not known or not detectable yet... ");
signalMsg = true;
}
else
{
APP_LOG_MSG(".");
}
HAL_Delay(1000);
}
else
{
quality_level_db = (int8_t)(-113 + 2 * quality_level);
APP_LOG_MSG("\r\nSignal Level: %d dBm\r\n", quality_level_db);
HAL_Delay(1000);
break;
}
}
tickcurrent = HAL_GetTick() - tickstart;
}
tickcurrent = HAL_GetTick() - tickstart;
while( (tickcurrent < registration_timeout_msec) || (registration_timeout_sec == LTE_COMMS_MAX_DELAY) )
{
/* Attach the MT to the backet domain service */
if (EG91_PSAttach(&Eg91Obj) == EG91_RETURN_OK)
{
APP_DEBUG_MSG("Packet Switched attachement succeeded\r\n");
break;
}
else
{
/* Start an Automatic PLMN selection */
attRetry++;
if (attRetry == 1)
{
APP_DEBUG_MSG("Trying an automatic registration. It may take until 3 minutes, please wait ...\r\n");
if (EG91_RETURN_OK != EG91_AutomaticPlmnSelection(&Eg91Obj))
{
break;
}
else
{
if (attRetry > 4)
{
APP_DEBUG_MSG("Unrecoverable Error, PS attachement failed\r\n");
break;
}
}
}
HAL_Delay(1000);
}
tickcurrent = HAL_GetTick() - tickstart;
}
/* Check Packet Switched Registration */
ret = (LTE_Registatus_t) EG91_GetPsNetworkRegistrationStatus(&Eg91Obj);
APP_DEBUG_MSG("Packet Switch Registration: %d\r\n", ret);
if ( (ret == LTE_REGISTATUS_HOME_NETWORK) || (ret == LTE_REGISTATUS_ROAMING) )
{
tickcurrent = HAL_GetTick() - tickstart;
APP_DEBUG_MSG("Registation done in %lu ms\r\n", tickcurrent);
}
}
else
{
if (init_status == EG91_INIT_RET_SIM_ERR)
{
sim_tmp = Eg91Obj.SimInfo.SimStatus;
if (sim_tmp == EG91_OPERATION_NOT_ALLOW)
{
ret = LTE_REGISTATUS_OP_NOT_ALLOWED;
}
else
{
ret = (LTE_Registatus_t) Eg91Obj.SimInfo.SimStatus;
}
}
else
{
ret = LTE_REGISTATUS_ERROR; /* Generic e.g. module does not respond to AT command */
}
}
}
return ret;
}
LTE_Ret_t LTE_GetSignalQualityStatus(int32_t *qValue)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_GetSignalQualityStatus(&Eg91Obj, qValue) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_ListOperators(char *operator)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_ListOperators(&Eg91Obj, operator) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_GetCurrentOperator (char *operator, int32_t bufSize)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_GetCurrentOperator(&Eg91Obj, operator, bufSize) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_ForceOperator(int32_t code)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_ForceOperator(&Eg91Obj, code) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_ConfigureAP(uint8_t contextType, const char *apn, const char *username,
const char *password, uint8_t authenticationMode)
{
LTE_Ret_t ret = LTE_RET_ERROR;
EG91_APConfig_t apConfig;
apConfig.ContextID = LTE_CONTEXT_1;
strncpy((char *)apConfig.ApnString, (char *)apn, EG91_MAX_APN_NAME_SIZE);
strncpy((char *)apConfig.Username, (char *)username, EG91_MAX_USER_NAME_SIZE);
strncpy((char *)apConfig.Password, (char *)password, EG91_MAX_PSW_NAME_SIZE);
apConfig.Authentication = (EG91_Authent_t)authenticationMode;
if (EG91_ConfigureAP(&Eg91Obj, &apConfig) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_Connect(void)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_Activate(&Eg91Obj, LTE_CONTEXT_1) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_Disconnect(void)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_Deactivate(&Eg91Obj, LTE_CONTEXT_1) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_APState_t LTE_isConnected(void)
{
return (LTE_APState_t) EG91_IsActivated(&Eg91Obj, LTE_CONTEXT_1);
}
LTE_Ret_t LTE_GetActiveIpAddress(char * ipAddrStr, uint8_t *ipAddrInt)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_GetActiveIpAddresses(&Eg91Obj, ipAddrStr, ipAddrInt) == LTE_RET_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_Ping(char *address, uint16_t count, uint16_t timeout)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_Ping(&Eg91Obj,LTE_CONTEXT_1, address, count, timeout) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_GetHostAddress(const char *address, uint8_t *ipaddr)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_DNS_LookUp(&Eg91Obj, LTE_CONTEXT_1, address, ipaddr) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_StartClientConnection(uint32_t socket, LTE_Protocol_t type, const char *url,
uint8_t *ipaddr, uint16_t port, uint16_t local_port)
{
LTE_Ret_t ret = LTE_RET_ERROR;
char converted_ipaddr[16] = { 0 };
EG91_Conn_t conn;
int random_number = 0;
conn.ConnectID = socket;
conn.RemotePort = port;
#ifdef ACCESS_MODE_DIRECT_PUSH
conn.AccessMode = EG91_DIRECT_PUSH;
#else
conn.AccessMode = EG91_BUFFER_MODE;
#endif
if (local_port != 0)
{
conn.LocalPort = local_port;
}
else
{
if(rnglocalport == 0)
{
random_number = rand();
rnglocalport = ((uint16_t)(random_number & 0xFFFF) >> 2) + 49152;
}
else
{
rnglocalport += 1;
}
if (rnglocalport < 49152) /* Wrap around */
{
rnglocalport = 49152;
}
conn.LocalPort = rnglocalport;
}
switch (type)
{
case LTE_TCP_PROTOCOL:
conn.Type = EG91_TCP_CONNECTION;
break;
case LTE_UDP_PROTOCOL:
conn.Type = EG91_UDP_CONNECTION;
break;
default:
conn.Type = LTE_RET_NOT_SUPPORTED;
break;
}
if (ret != LTE_RET_NOT_SUPPORTED)
{
if (url == NULL)
{
LTE_ConvertIpAddrToString(ipaddr, converted_ipaddr);
conn.Url = converted_ipaddr;
}
else
{
conn.Url = (char*)url;
}
if (EG91_OpenClientConnection(&Eg91Obj, LTE_CONTEXT_1, &conn) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
}
return ret;
}
LTE_Ret_t LTE_StopClientConnection(uint32_t socket)
{
LTE_Ret_t ret = LTE_RET_ERROR;
EG91_Conn_t conn;
conn.ConnectID = socket;
if (EG91_CloseClientConnection(&Eg91Obj, &conn) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_StartServerConnection(uint32_t socket, LTE_Protocol_t type, uint16_t port, uint16_t local_port)
{
return LTE_RET_NOT_SUPPORTED;
}
LTE_Ret_t LTE_StopServerConnection(uint32_t socket)
{
return LTE_RET_NOT_SUPPORTED;
}
LTE_SendStatus_t LTE_SendData(uint32_t socket, uint8_t *pdata, uint16_t reqLen, uint16_t *sentDataLen, uint32_t timeout)
{
LTE_SendStatus_t ret = LTE_SEND_ERROR;
EG91_SendRet_t status;
status = EG91_SendData(&Eg91Obj, socket, pdata, reqLen, sentDataLen, timeout);
if (status == EG91_SEND_RET_SENT)
{
ret = LTE_SEND_OK;
} else if (status == EG91_SEND_RET_BUF_FULL)
{
ret = LTE_SEND_BUF_FULL;
}
return ret;
}
LTE_Ret_t LTE_ReceiveData(uint32_t socket, uint8_t *pdata, uint16_t reqLen, uint16_t *rcvDataLen, uint32_t timeout)
{
LTE_Ret_t ret = LTE_RET_ERROR;
EG91_ReceiveRet_t result;
result = EG91_ReceiveData(&Eg91Obj, socket, pdata, reqLen, rcvDataLen, timeout);
if ((result == EG91_RECEIVE_RET_OK) || (result == EG91_RECEIVE_RET_INCOMPLETE))
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_RetrieveLastErrorDetails(char *errorStr)
{
LTE_Ret_t ret = LTE_RET_ERROR;
char errStr[EG91_ERROR_STRING_SIZE];
memset(errStr, 0, EG91_ERROR_STRING_SIZE);
if (EG91_RetrieveLastErrorDetails(&Eg91Obj, errStr) == EG91_RETURN_OK)
{
strncpy(errorStr, errStr, MIN(LTE_ERROR_STRING, EG91_ERROR_STRING_SIZE));
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_PowerOff(void)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (EG91_PowerDown(&Eg91Obj) == EG91_RETURN_OK)
{
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_GetModuleFirmwareRevision(char *rev)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (Eg91Obj.FW_Rev != NULL)
{
strncpy(rev, (char*)Eg91Obj.FW_Rev, MIN(LTE_FW_REV_SIZE, EG91_FW_REV_SIZE));
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_GetModuleID(char *productId)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (Eg91Obj.ProductID != NULL)
{
strncpy(productId, (char*)Eg91Obj.ProductID, MIN(LTE_PROD_ID_SIZE, EG91_PROD_ID_SIZE));
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_GetModuleName(char *moduleName)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (Eg91Obj.Manufacturer != NULL)
{
strncpy(moduleName, (char*)Eg91Obj.Manufacturer, MIN(LTE_MAN_SIZE, EG91_MFC_SIZE));
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_GetSimId(char *simId)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (Eg91Obj.SimInfo.ICCID != NULL)
{
strncpy(simId, (char*)Eg91Obj.SimInfo.ICCID, MIN(LTE_ICCID_SIZE, EG91_ICCID_SIZE));
ret = LTE_RET_OK;
}
return ret;
}
LTE_Ret_t LTE_GetIMEI(char *imei)
{
LTE_Ret_t ret = LTE_RET_ERROR;
if (Eg91Obj.Imei != NULL)
{
strncpy(imei, (char*)Eg91Obj.Imei, MIN(LTE_IMEI_SIZE, EG91_IMEI_SIZE));
ret = LTE_RET_OK;
}
return ret;
}

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "icache.h"
#include "usart.h"
#include "rtc.h"
#include "gpio.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include <stdbool.h>
#include "lte_comms.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_LPUART1_UART_Init();
MX_USART1_UART_Init();
MX_RTC_Init();
MX_ICACHE_Init();
/* USER CODE BEGIN 2 */
Network_Init();
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
uint8_t counter = 0;
uint8_t shut_lte_off = 1;
while (1)
{
if (shut_lte_off == 1)
{
LTE_HardwarePowerDown();
APP_LOG_MSG("LTE TEST DONE\r\n");
shut_lte_off = 0;
}
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSEDiv = RCC_HSE_DIV1;
RCC_OscInitStruct.LSIState = RCC_LSI1_ON;
RCC_OscInitStruct.LSIDiv = RCC_LSI_DIV1;
RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL1.PLLM = 2;
RCC_OscInitStruct.PLL1.PLLN = 8;
RCC_OscInitStruct.PLL1.PLLP = 2;
RCC_OscInitStruct.PLL1.PLLQ = 2;
RCC_OscInitStruct.PLL1.PLLR = 2;
RCC_OscInitStruct.PLL1.PLLFractional = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_PCLK7|RCC_CLOCKTYPE_HCLK5;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB7CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.AHB5_PLL1_CLKDivider = RCC_SYSCLK_PLL1_DIV2;
RCC_ClkInitStruct.AHB5_HSEHSI_CLKDivider = RCC_SYSCLK_HSEHSI_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file rtc.c
* @brief This file provides code for the configuration
* of the RTC instances.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "rtc.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
RTC_HandleTypeDef hrtc;
/* RTC init function */
void MX_RTC_Init(void)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
RTC_PrivilegeStateTypeDef privilegeState = {0};
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/** Initialize RTC Only
*/
hrtc.Instance = RTC;
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
hrtc.Init.AsynchPrediv = 127;
hrtc.Init.SynchPrediv = 255;
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE;
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE;
hrtc.Init.BinMode = RTC_BINARY_NONE;
if (HAL_RTC_Init(&hrtc) != HAL_OK)
{
Error_Handler();
}
privilegeState.rtcPrivilegeFull = RTC_PRIVILEGE_FULL_NO;
privilegeState.backupRegisterPrivZone = RTC_PRIVILEGE_BKUP_ZONE_NONE;
privilegeState.backupRegisterStartZone2 = RTC_BKP_DR0;
privilegeState.backupRegisterStartZone3 = RTC_BKP_DR0;
if (HAL_RTCEx_PrivilegeModeSet(&hrtc, &privilegeState) != HAL_OK)
{
Error_Handler();
}
/** Enable the WakeUp
*/
if (HAL_RTCEx_SetWakeUpTimer(&hrtc, 0, RTC_WAKEUPCLOCK_RTCCLK_DIV16) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle)
{
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(rtcHandle->Instance==RTC)
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
/* RTC clock enable */
__HAL_RCC_RTCAPB_CLK_ENABLE();
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle)
{
if(rtcHandle->Instance==RTC)
{
/* USER CODE BEGIN RTC_MspDeInit 0 */
/* USER CODE END RTC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_RTCAPB_CLK_DISABLE();
/* USER CODE BEGIN RTC_MspDeInit 1 */
/* USER CODE END RTC_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32wbaxx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_RCC_HSEM_CLK_ENABLE();
/* System interrupt init*/
/* Peripheral interrupt init */
/* HSEM_IRQn interrupt configuration */
HAL_NVIC_SetPriority(HSEM_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(HSEM_IRQn);
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32wbaxx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32wbaxx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "gpio.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern UART_HandleTypeDef huart1;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32WBAxx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32wbaxx.s). */
/******************************************************************************/
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
/* USER CODE BEGIN USART1_IRQn 0 */
HAL_GPIO_TogglePin(STATUS_LED_GPIO_Port, STATUS_LED_Pin);
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
/**
* @brief This function handles HSEM non-secure global interrupt.
*/
void HSEM_IRQHandler(void)
{
/* USER CODE BEGIN HSEM_IRQn 0 */
/* USER CODE END HSEM_IRQn 0 */
HAL_HSEM_IRQHandler();
/* USER CODE BEGIN HSEM_IRQn 1 */
/* USER CODE END HSEM_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/**
******************************************************************************
* @file system_stm32wbaxx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
*
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32wbaxx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32wbaxx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL1_SRC | No clock
*-----------------------------------------------------------------------------
* PLL1_M | 1
*-----------------------------------------------------------------------------
* PLL1_N | 128
*-----------------------------------------------------------------------------
* PLL1_P | 1
*-----------------------------------------------------------------------------
* PLL1_Q | 1
*-----------------------------------------------------------------------------
* PLL1_R | 1
*-----------------------------------------------------------------------------
* Require 48MHz for | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup STM32WBAxx_system
* @{
*/
/** @addtogroup STM32WBAxx_System_Private_Includes
* @{
*/
#include "stm32wbaxx.h"
#include <math.h>
/**
* @}
*/
/** @addtogroup STM32WBAxx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32WBAxx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (32000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/*!< The VTOR location information is based on information from the linker with a dependency
on the IDE, the cortex register is updated using the INTVECT_START.
*/
#if defined(__ICCARM__)
extern uint32_t __vector_table;
#define INTVECT_START ((uint32_t)& __vector_table)
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern void * __Vectors;
#define INTVECT_START ((uint32_t) & __Vectors)
#elif defined(__GNUC__)
extern void * g_pfnVectors;
#define INTVECT_START ((uint32_t)& g_pfnVectors)
#endif /* __ICCARM__*/
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32WBAxx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32WBAxx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000U; /* The HSI16 is used as system clock source after startup from reset, configured at 16 MHz. */
const uint8_t AHBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint8_t AHB5PrescTable[8] = {1U, 1U, 1U, 1U, 2U, 3U, 4U, 6U};
/**
* @}
*/
/** @addtogroup STM32WBAxx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32WBAxx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
#if defined(STM32WBAXX_SI_CUT1_0)
__IO uint32_t timeout_cpu_cycles;
#endif
#if defined(STM32WBAXX_SI_CUT1_0) || defined (VREFBUF)
__IO uint32_t tmpreg;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
#endif
/* Configure the Vector Table location -------------------------------------*/
SCB->VTOR = INTVECT_START;
#if defined(STM32WBAXX_SI_CUT1_0)
/* Work-around for ADC peripheral issue possibly impacting system
power consumption.
Refer to STM32WBA errata sheet item "HSI16 clock cannot be stopped when
used as kernel clock by ADC".
Actions: Perform a ADC activation sequence in order to update state
of internal signals.
*/
/* Enable ADC kernel clock */
SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN);
(void)tmpreg;
/* Enable ADC */
SET_BIT(ADC4->CR, ADC_CR_ADEN);
/* Poll for ADC ready */
/* Set timeout 2 ADC clock cycles */
/* Note: Approximative computation and timeout execution not taking into
account processing CPU cycles */
timeout_cpu_cycles = 2;
while (READ_BIT(ADC4->ISR, ADC_ISR_ADRDY) == 0U)
{
timeout_cpu_cycles--;
if(timeout_cpu_cycles == 0U)
{
break;
}
}
/* Disable ADC */
SET_BIT(ADC4->CR, ADC_CR_ADDIS);
/* Poll for ADC disable is effective */
/* Set timeout 6 ADC clock cycles */
/* Note: Approximative computation and timeout execution not taking into
account processing CPU cycles */
timeout_cpu_cycles = 6;
while (READ_BIT(ADC4->CR, ADC_CR_ADEN) != 0U)
{
timeout_cpu_cycles--;
if(timeout_cpu_cycles == 0U)
{
break;
}
}
/* Disable ADC internal voltage regulator */
CLEAR_BIT(ADC4->CR, ADC_CR_ADVREGEN);
/* Disable ADC kernel clock */
CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN);
#endif
#if defined (VREFBUF)
/* Work-around for VREFBUF peripheral issue.
Refer to STM32WBA errata sheet item "VREF BUFF cannot be trimmed by EngiBit".
Actions: Our SW copies the TRIM V11 (R1) in VREFBUF CCR (to guarantee the correct start
trim instead the current bad value 111111).
*/
/* Enable VREFBUF kernel clock */
SET_BIT(RCC->APB7ENR, RCC_APB7ENR_VREFEN);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_VREFEN);
(void)tmpreg;
/* Set TRIM V11 (R1) value */
MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, ((*(uint32_t *)(FLASH_ENGY_BASE + 0x2ABUL)) & 0x3FUL));
/* Disable VREFBUF kernel clock */
CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_VREFEN);
#endif /* VREFBUF */
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL1, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) multiplied/divided by the PLL1 factors.
*
* (**) HSI_VALUE is a constant defined in STM32WBAxx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in STM32WBAxx_hal.h file (default value
* 32 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp1;
uint32_t tmp2;
uint32_t pllsource;
uint32_t pllr;
uint32_t pllm;
uint32_t plln;
float_t fracn;
float_t pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR1 & RCC_CFGR1_SWS)
{
case RCC_CFGR1_SWS_1: /* HSE used as system clock source */
SystemCoreClock = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos));
break;
case (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1): /* PLL1 used as system clock source */
/* PLL_VCO = (PLLsource / PLLM) * PLLN * FractionnalPart
SYSCLK = PLL_VCO / PLLR */
/* Get PLL1 CFGR and DIVR register values */
tmp1 = RCC->PLL1CFGR;
tmp2 = RCC->PLL1DIVR;
/* Retrieve PLL1 multiplication factor and divider */
pllm = ((tmp1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
plln = (tmp2 & RCC_PLL1DIVR_PLL1N) + 1U;
pllr = ((tmp2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U;
/* Check if fractional part is enable */
if ((tmp1 & RCC_PLL1CFGR_PLL1FRACEN) != 0x00u)
{
fracn = (float_t)((uint32_t)((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos));
}
else
{
fracn = (float_t)0U;
}
/* determine PLL source */
pllsource = (tmp1 & RCC_PLL1CFGR_PLL1SRC);
switch (pllsource)
{
/* HSI used as PLL1 clock source */
case RCC_PLL1CFGR_PLL1SRC_1:
tmp1 = HSI_VALUE;
break;
/* HSE used as PLL1 clock source */
case (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1):
tmp1 = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos));
break;
default:
tmp1 = 0U;
break;
}
/* Compute VCO output frequency */
pllvco = ((float_t) tmp1 / (float_t)pllm) * (((float_t)plln + (float_t)(fracn / (float_t)0x2000U)));
SystemCoreClock = (uint32_t)((float_t)(pllvco / (float_t)pllr));
break;
case 0x00u: /* HSI used as system clock source */
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp1 = AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp1;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file usart.c
* @brief This file provides code for the configuration
* of the USART instances.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "usart.h"
/* USER CODE BEGIN 0 */
#include <stdbool.h>
#define RING_BUFFER_SIZE 1500
#define UART_RX_BUF_SIZE 128
typedef struct
{
uint8_t data[RING_BUFFER_SIZE];
uint16_t tail;
uint16_t head;
} ringbuffer_t;
ringbuffer_t UART_RxData;
uint8_t UART1_RxByte; // For single-byte interrupt reception
uint8_t UART1_RxBuffer[UART_RX_BUF_SIZE]; // Circular or linear buffer
volatile uint16_t uart1_rx_index = 0;
volatile bool uart1_msg_ready = false;
/* USER CODE END 0 */
UART_HandleTypeDef hlpuart1;
UART_HandleTypeDef huart1;
/* LPUART1 init function */
void MX_LPUART1_UART_Init(void)
{
/* USER CODE BEGIN LPUART1_Init 0 */
/* USER CODE END LPUART1_Init 0 */
/* USER CODE BEGIN LPUART1_Init 1 */
/* USER CODE END LPUART1_Init 1 */
hlpuart1.Instance = LPUART1;
hlpuart1.Init.BaudRate = 115200;
hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
hlpuart1.Init.StopBits = UART_STOPBITS_1;
hlpuart1.Init.Parity = UART_PARITY_NONE;
hlpuart1.Init.Mode = UART_MODE_TX_RX;
hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
if (HAL_UART_Init(&hlpuart1) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN LPUART1_Init 2 */
/* USER CODE END LPUART1_Init 2 */
}
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
/* USER CODE BEGIN USART1_Init 0 */
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE;
huart1.Init.Mode = UART_MODE_TX_RX;
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART1_Init 2 */
UART_RxData.head = 0;
UART_RxData.tail = 0;
HAL_UART_Receive_IT(&huart1, (uint8_t*)&UART_RxData.data[UART_RxData.tail], 1);
/* USER CODE END USART1_Init 2 */
}
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(uartHandle->Instance==LPUART1)
{
/* USER CODE BEGIN LPUART1_MspInit 0 */
/* USER CODE END LPUART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK7;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
/* LPUART1 clock enable */
__HAL_RCC_LPUART1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**LPUART1 GPIO Configuration
PB11 ------> LPUART1_TX
PA10 ------> LPUART1_RX
*/
GPIO_InitStruct.Pin = DEBUG_TX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
HAL_GPIO_Init(DEBUG_TX_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = DEBUG_RX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
HAL_GPIO_Init(DEBUG_RX_GPIO_Port, &GPIO_InitStruct);
/* USER CODE BEGIN LPUART1_MspInit 1 */
/* USER CODE END LPUART1_MspInit 1 */
}
else if(uartHandle->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**USART1 GPIO Configuration
PB12 ------> USART1_TX
PA8 ------> USART1_RX
*/
GPIO_InitStruct.Pin = LTE_TX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
HAL_GPIO_Init(LTE_TX_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = LTE_RX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
HAL_GPIO_Init(LTE_RX_GPIO_Port, &GPIO_InitStruct);
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
{
if(uartHandle->Instance==LPUART1)
{
/* USER CODE BEGIN LPUART1_MspDeInit 0 */
/* USER CODE END LPUART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_LPUART1_CLK_DISABLE();
/**LPUART1 GPIO Configuration
PB11 ------> LPUART1_TX
PA10 ------> LPUART1_RX
*/
HAL_GPIO_DeInit(DEBUG_TX_GPIO_Port, DEBUG_TX_Pin);
HAL_GPIO_DeInit(DEBUG_RX_GPIO_Port, DEBUG_RX_Pin);
/* USER CODE BEGIN LPUART1_MspDeInit 1 */
/* USER CODE END LPUART1_MspDeInit 1 */
}
else if(uartHandle->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspDeInit 0 */
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
PB12 ------> USART1_TX
PA8 ------> USART1_RX
*/
HAL_GPIO_DeInit(LTE_TX_GPIO_Port, LTE_TX_Pin);
HAL_GPIO_DeInit(LTE_RX_GPIO_Port, LTE_RX_Pin);
/* USART1 interrupt Deinit */
HAL_NVIC_DisableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
int8_t LTE_UART_SetBaudrate(uint32_t baudrate)
{
HAL_UART_DeInit(&huart1);
huart1.Init.BaudRate = baudrate;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
return -1;
}
UART_RxData.head = 0;
UART_RxData.tail = 0;
HAL_UART_Receive_IT(&huart1, (uint8_t *)&UART_RxData.data[UART_RxData.tail], 1);
return 0;
}
void LTE_UART_FlushBuffer(void)
{
memset(UART_RxData.data, 0, RING_BUFFER_SIZE);
UART_RxData.head = 0;
UART_RxData.tail = 0;
}
int16_t LTE_UART_SendData(uint8_t *pData, uint16_t length)
{
if(HAL_UART_Transmit(&huart1, (uint8_t*)pData, length, HAL_MAX_DELAY) != HAL_OK)
{
return -1;
}
return 0;
}
int16_t LTE_UART_ReceiveSingleData(uint8_t *pSingleData)
{
if (UART_RxData.head != UART_RxData.tail)
{
*pSingleData = UART_RxData.data[UART_RxData.head++];
if (UART_RxData.head >= RING_BUFFER_SIZE)
{
UART_RxData.head = 0;
}
} else
{
return -1;
}
return 0;
}
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
if (++UART_RxData.tail >= RING_BUFFER_SIZE)
{
UART_RxData.tail = 0;
}
HAL_UART_Receive_IT(huart, (uint8_t*) &UART_RxData.data[UART_RxData.tail], 1);
}
#pragma module_name = "?__write"
size_t __write(int handle, const unsigned char *buffer, size_t size)
{
if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
return _LLIO_ERROR;
for (size_t i = 0; i < size; ++i)
{
HAL_UART_Transmit(&hlpuart1, (uint8_t *)&buffer[i], 1, HAL_MAX_DELAY);
}
return size;
}
void LTE_ATSendCommand(const char *cmd)
{
HAL_UART_Transmit(&huart1, (uint8_t *)cmd, strlen(cmd), 1000);
}
/* For Testing Purposes ONLY */
void LTE_SendATCommand_Test(void)
{
const char *cmd = "AT\r\n";
uint8_t rx_byte;
uint8_t rx_buff[100] = {0};
int idx = 0;
uint32_t startTick;
// Transmit AT Command
if (HAL_UART_Transmit(&huart1, (uint8_t *)cmd, strlen(cmd), 1000) != HAL_OK)
{
APP_ERROR_MSG("UART TX Failed\r\n");
return;
}
// Wait and read each byte until timeout or buffer full
startTick = HAL_GetTick();
while ((HAL_GetTick() - startTick) < 1000 && idx < sizeof(rx_buff) - 1)
{
if (HAL_UART_Receive(&huart1, &rx_byte, 1, 10) == HAL_OK)
{
rx_buff[idx++] = rx_byte;
// Reset timeout if still receiving
startTick = HAL_GetTick();
}
}
rx_buff[idx] = '\0'; // Null-terminate the received string
APP_LTE_MSG(" %s\r\n", rx_buff);
}
/* USER CODE END 1 */

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<?xml version="1.0" encoding="UTF-8"?>
<workspace>
<project>
<path>$WS_DIR$\WiseEye-LTE.ewp</path>
</project>
<batchBuild />
</workspace>

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<?xml version="1.0" encoding="UTF-8"?>
<BuildDb>
<Tool>
<Name>linker</Name>
<Parent>
<Path>C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Exe\WiseEye-LTE.out</Path>
<Output>
<Path>C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\List\WiseEye-LTE.map</Path>
</Output>
</Parent>
</Tool>
</BuildDb>

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# ninja log v5
913 1359 7757315760265676 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/main.o d7bb6238eda97835
25 332 7757315750015898 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/stm32wbaxx_it.o b1492b16968ccb3a
17 484 7757315751316791 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/usart.o fc760e94c1ec22d6
362 909 7757315755758306 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_gpio.o d8794485a89ad2f
14 307 7757315749815823 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/CMSIS_6603591812247902717.dir/system_stm32wbaxx.o 3515f0d237f25ee1
860 1250 7757315759040405 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/icache.o e5fc2cc393d04836
488 1035 7757315756945716 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_pwr_ex.o d67c119bfda1211b
7 357 7757315750225023 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/gpio.o 106e1b368ea961f6
850 1217 7757315758891650 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/stm32wbaxx_hal_msp.o 22404d930743ee6d
20 455 7757315751154916 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal.o 2bba1bc5ffab2df8
1253 1282 7757315759666926 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/EWARM_18443280873093131863.dir/startup_stm32wba52xx.o 980d1ae4b050ec79
336 856 7757315755117837 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_exti.o 7d767c0d10691ecd
10 394 7757315750663175 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_cortex.o 3de086e6b4548ee2
35 444 7757315751113968 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_flash.o 737b74d2ab05fc2f
448 954 7757315756143436 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_icache.o e8f7a6841210f89c
458 983 7757315756237054 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_pwr.o a13a8cf6c7fd9ba5
310 996 7757315756495286 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_flash_ex.o 784741301e8d236e
30 808 7757315754780026 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_dma.o bb545f39d3ef5f89
1244 1884 7757315765514679 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rcc_ex.o 36810b1623d15a67
1285 1888 7757315765534765 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_uart_ex.o ca08aa8c8f1e31a2
988 2079 7757315767519955 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rcc.o 14ef3783a91bbc4e
3231 3251 7757315779337033 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Exe/WiseEye-LTE.hex 39975d729c88188e
40 1735 7757315764023161 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_dma_ex.o 8a76874fecc684f0
1222 3087 7757315777561982 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_uart.o 41c927090a97bf66
3092 3228 7757315779017690 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Exe/WiseEye-LTE.out 67e126dbefc696f
812 1239 7757315758996926 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/rtc.o c6ac9732a0803d21
397 847 7757315755117837 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_hsem.o 778dcbb8e1aa00ca
1001 1833 7757315765048275 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rtc.o da179d1fd6bd206c
1041 2017 7757315766868318 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rtc_ex.o d8c2edea8f75509c
2 1476 7757315761417737 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/eg91.o 238ab17cd6d129e4
958 1787 7757315764596475 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/lte_comms.o 2b72a3fbf43401b8
28 1783 7757317473875002 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal.o 2bba1bc5ffab2df8
16 1970 7757317475721387 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/stm32wbaxx_it.o b1492b16968ccb3a
20 2023 7757317476321785 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_cortex.o 3de086e6b4548ee2
24 2034 7757317476367025 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/CMSIS_6603591812247902717.dir/system_stm32wbaxx.o 3515f0d237f25ee1
10 2064 7757317476621991 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/gpio.o 106e1b368ea961f6
12 2093 7757317476823301 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/usart.o fc760e94c1ec22d6
36 2163 7757317477652192 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_exti.o 7d767c0d10691ecd
1787 2250 7757317478542119 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_flash.o 737b74d2ab05fc2f
40 2409 7757317480174383 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_dma.o bb545f39d3ef5f89
2070 2461 7757317480652165 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_hsem.o 778dcbb8e1aa00ca
2039 2499 7757317481016294 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_pwr_ex.o d67c119bfda1211b
2028 2518 7757317481121226 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_pwr.o a13a8cf6c7fd9ba5
2097 2582 7757317481872127 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_gpio.o d8794485a89ad2f
2167 2613 7757317482122049 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_icache.o e8f7a6841210f89c
1974 2647 7757317482325324 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_flash_ex.o 784741301e8d236e
2254 2657 7757317482275617 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/stm32wbaxx_hal_msp.o 22404d930743ee6d
2413 2789 7757317483993572 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/icache.o e5fc2cc393d04836
2 2800 7757317483925500 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/eg91.o 238ab17cd6d129e4
2805 2830 7757317484521828 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/EWARM_18443280873093131863.dir/startup_stm32wba52xx.o 980d1ae4b050ec79
2466 2858 7757317484620720 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/rtc.o c6ac9732a0803d21
2522 2882 7757317484848330 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/main.o d7bb6238eda97835
31 3141 7757317487430019 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_dma_ex.o 8a76874fecc684f0
2502 3219 7757317488275783 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/lte_comms.o 2b72a3fbf43401b8
2624 3259 7757317488651231 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rcc_ex.o 36810b1623d15a67
2586 3352 7757317489621454 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rtc.o da179d1fd6bd206c
2834 3376 7757317489873496 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_uart_ex.o ca08aa8c8f1e31a2
2662 3507 7757317491125792 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rtc_ex.o d8c2edea8f75509c
2793 3731 7757317493372244 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rcc.o 14ef3783a91bbc4e
2651 4446 7757317500430692 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_uart.o 41c927090a97bf66
4452 4579 7757317501925662 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Exe/WiseEye-LTE.out 67e126dbefc696f
4586 4603 7757317502279565 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Exe/WiseEye-LTE.hex 39975d729c88188e
19 329 7757319035449612 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/CMSIS_6603591812247902717.dir/system_stm32wbaxx.o 3515f0d237f25ee1
26 356 7757319035643378 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/stm32wbaxx_it.o b1492b16968ccb3a
2 403 7757319036209637 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/gpio.o 106e1b368ea961f6
22 452 7757319036689535 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_cortex.o 3de086e6b4548ee2
12 479 7757319036831411 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal.o 2bba1bc5ffab2df8
36 500 7757319037048963 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_flash.o 737b74d2ab05fc2f
14 553 7757319037739826 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/usart.o fc760e94c1ec22d6
41 843 7757319040604345 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_dma.o bb545f39d3ef5f89
455 873 7757319040761952 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_hsem.o 778dcbb8e1aa00ca
407 902 7757319041081491 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_pwr_ex.o d67c119bfda1211b
360 912 7757319041081491 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_exti.o 7d767c0d10691ecd
483 935 7757319041262507 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_icache.o e8f7a6841210f89c
504 1006 7757319041774557 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_pwr.o a13a8cf6c7fd9ba5
332 1017 7757319042127579 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_flash_ex.o 784741301e8d236e
557 1089 7757319043088905 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_gpio.o d8794485a89ad2f
847 1234 7757319044492289 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/icache.o e5fc2cc393d04836
943 1310 7757319045249180 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/stm32wbaxx_hal_msp.o 22404d930743ee6d
916 1320 7757319045266692 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/rtc.o c6ac9732a0803d21
907 1343 7757319045388669 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/main.o d7bb6238eda97835
1346 1373 7757319046051894 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/EWARM_18443280873093131863.dir/startup_stm32wba52xx.o 980d1ae4b050ec79
9 1458 7757319046688067 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/eg91.o 238ab17cd6d129e4
1010 1639 7757319048564776 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rcc_ex.o 36810b1623d15a67
877 1644 7757319048564776 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/Core_13247989168731456611.dir/lte_comms.o 2b72a3fbf43401b8
31 1721 7757319049392531 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_dma_ex.o 8a76874fecc684f0
1022 1807 7757319050231883 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rtc.o da179d1fd6bd206c
1325 1897 7757319051132476 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_uart_ex.o ca08aa8c8f1e31a2
1093 1982 7757319051962711 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rtc_ex.o d8c2edea8f75509c
1314 2299 7757319055131708 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_rcc.o 14ef3783a91bbc4e
1238 3036 7757319062434339 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Obj/STM32WBAxx_HAL_Driver_814230103969653557.dir/stm32wbaxx_hal_uart.o 41c927090a97bf66
3042 3170 7757319063851900 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Exe/WiseEye-LTE.out 67e126dbefc696f
3180 3199 7757319064330718 C:/Users/Admin/Documents/.Projects/7. Cellular Relay Controller/LTE-Code/WiseEye-LTE/EWARM/WiseEye-LTE/Exe/WiseEye-LTE.hex 39975d729c88188e

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###############################################################################
#
# IAR ELF Linker V9.40.2.374/W64 for ARM 01/Aug/2025 14:11:46
# Copyright 2007-2023 IAR Systems AB.
#
# Output file =
# C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Exe\WiseEye-LTE.out
# Map file =
# C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\List\WiseEye-LTE.map
# Command line =
# -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Exe\WiseEye-LTE.out.rsp"
# ("C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\eg91.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\gpio.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\icache.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\lte_comms.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\main.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\rtc.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\EWARM_18443280873093131863.dir\startup_stm32wba52xx.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_cortex.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_dma.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_dma_ex.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_exti.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_flash.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_flash_ex.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_gpio.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_hsem.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_icache.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\stm32wbaxx_hal_msp.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_pwr.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_pwr_ex.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_rcc.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_rcc_ex.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_rtc.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_rtc_ex.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_uart.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir\stm32wbaxx_hal_uart_ex.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\stm32wbaxx_it.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\CMSIS_6603591812247902717.dir\system_stm32wbaxx.o"
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir\usart.o"
# --redirect _Printf=_PrintfFullNoMb --redirect _Scanf=_ScanfFullNoMb
# --no_out_extension -o "C:\Users\Admin\Documents\.Projects\7. Cellular
# Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Exe\WiseEye-LTE.out"
# --map "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\List\WiseEye-LTE.map"
# --config "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM/stm32wba52xx_flash.icf"
# --semihosting --entry __iar_program_start --vfe --text_out locale
# --cpu=Cortex-M33.no_dsp.no_se --fpu=VFPv5_sp) --dependencies=n
# "C:\Users\Admin\Documents\.Projects\7. Cellular Relay
# Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Exe\WiseEye-LTE.out.iar_deps"
#
###############################################################################
*******************************************************************************
*** RUNTIME MODEL ATTRIBUTES
***
CppFlavor = *
__CPP_Runtime = 1
__SystemLibrary = DLib
__dlib_version = 6
*******************************************************************************
*** HEAP SELECTION
***
The basic heap was selected because --advanced_heap
was not specified and the application did not appear to
be primarily optimized for speed.
*******************************************************************************
*** PLACEMENT SUMMARY
***
"A0": place at address 0x800'0000 { ro section .intvec };
"P1": place in [from 0x800'0000 to 0x80f'ffff] { ro };
define block CSTACK with size = 1K, alignment = 8 { };
define block HEAP with size = 512, alignment = 8 { };
"P2": place in [from 0x2000'0000 to 0x2000'ffff] {
rw, block CSTACK, block HEAP };
initialize by copy { rw };
Section Kind Address Size Object
------- ---- ------- ---- ------
"A0": 0x15c
.intvec ro code 0x800'0000 0x15c startup_stm32wba52xx.o [3]
- 0x800'015c 0x15c
"P1": 0x5f80
.text ro code 0x800'015c 0xeca xprintffull_nomb.o [5]
.text ro code 0x800'1026 0x7e lz77_init_single.o [7]
.text ro code 0x800'10a4 0x16 strchr.o [7]
.rodata const 0x800'10ba 0x2 xlocale_c.o [5]
.text ro code 0x800'10bc 0x40 xfail_s.o [5]
.text ro code 0x800'10fc 0x14 strlen_small.o [7]
.text ro code 0x800'1110 0x58 memchr.o [7]
.text ro code 0x800'1168 0x18 ABImemcpy_small.o [7]
.text ro code 0x800'1180 0x70 frexp.o [6]
.text ro code 0x800'11f0 0x34 DblCmpLe.o [6]
.text ro code 0x800'1224 0x34 DblCmpGe.o [6]
.text ro code 0x800'1258 0x13a ldexp.o [6]
.rodata const 0x800'1392 0x2 xlocale_c.o [5]
.text ro code 0x800'1394 0x36 DblToS32.o [6]
.rodata const 0x800'13ca 0x1 xlocale_c.o [5]
.text ro code 0x800'13cc 0x22 S32ToDbl.o [6]
.text ro code 0x800'13f0 0x24e DblAddSub.o [6]
.text ro code 0x800'1640 0x246 DblDiv.o [6]
.text ro code 0x800'1888 0x22 DblToU32.o [6]
.text ro code 0x800'18ac 0x1c U32ToDbl.o [6]
.text ro code 0x800'18c8 0x1aa DblMul.o [6]
.text ro code 0x800'1a74 0x3c xlocale_c.o [5]
.text ro code 0x800'1ab0 0x106 I64DivMod_small.o [7]
.text ro code 0x800'1bb6 0x6 abort.o [5]
.text ro code 0x800'1bbc 0x2 I64DivZer.o [7]
.text ro code 0x800'1bc0 0x14 exit.o [8]
.text ro code 0x800'1bd4 0xe90 stm32wbaxx_hal_uart.o [4]
.text ro code 0x800'2a64 0x350 usart.o [2]
.text ro code 0x800'2db4 0xc stm32wbaxx_hal.o [4]
.text ro code 0x800'2dc0 0xbe stm32wbaxx_hal_dma.o [4]
.text ro code 0x800'2e7e 0x2 stm32wbaxx_hal_uart.o [4]
.text ro code 0x800'2e80 0x2 stm32wbaxx_hal_uart.o [4]
.text ro code 0x800'2e82 0x2 stm32wbaxx_hal_uart.o [4]
.text ro code 0x800'2e84 0x2 stm32wbaxx_hal_uart_ex.o [4]
.text ro code 0x800'2e86 0x2 stm32wbaxx_hal_uart_ex.o [4]
.text ro code 0x800'2e88 0x760 stm32wbaxx_hal_rcc.o [4]
.text ro code 0x800'35e8 0xcc main.o [2]
.text ro code 0x800'36b4 0xf8 stm32wbaxx_hal_uart_ex.o [4]
.text ro code 0x800'37ac 0x6 ABImemclr4.o [7]
.text ro code 0x800'37b4 0x208 stm32wbaxx_hal_rcc_ex.o [4]
.text ro code 0x800'39bc 0x128 stm32wbaxx_hal_cortex.o [4]
.text ro code 0x800'3ae4 0x264 stm32wbaxx_hal_gpio.o [4]
.text ro code 0x800'3d48 0x94 stm32wbaxx_hal.o [4]
.text ro code 0x800'3ddc 0x34 stm32wbaxx_hal.o [4]
.text ro code 0x800'3e10 0x144 gpio.o [2]
.text ro code 0x800'3f54 0xbc rtc.o [2]
.text ro code 0x800'4010 0x1e icache.o [2]
.text ro code 0x800'4030 0x3bc lte_comms.o [2]
.text ro code 0x800'43ec 0x28 printf.o [5]
.text ro code 0x800'4414 0x5c stm32wbaxx_hal_pwr_ex.o [4]
.text ro code 0x800'4470 0x32 ABImemset48.o [7]
.text ro code 0x800'44a4 0x104 system_stm32wbaxx.o [1]
.text ro code 0x800'45a8 0x40 stm32wbaxx_hal_msp.o [2]
.text ro code 0x800'45e8 0x28 stm32wbaxx_hal.o [4]
.text ro code 0x800'4610 0x14 memset.o [7]
.text ro code 0x800'4624 0x17c stm32wbaxx_hal_rtc.o [4]
.text ro code 0x800'47a0 0xc4 stm32wbaxx_hal_rtc_ex.o [4]
.text ro code 0x800'4864 0x38 stm32wbaxx_hal_icache.o [4]
.text ro code 0x800'489c 0x1e strncpy_small.o [7]
.text ro code 0x800'48bc 0x740 eg91.o [2]
.text ro code 0x800'4ffc 0x12 ABImemset_small.o [7]
.text ro code 0x800'500e 0x2c strstr.o [5]
.text ro code 0x800'503c 0x4c strtok.o [5]
.text ro code 0x800'5088 0x152 iar_Stoulx.o [5]
.text ro code 0x800'51da 0x22 strspn.o [5]
.text ro code 0x800'51fc 0x22 strcspn.o [5]
.text ro code 0x800'521e 0x14 isspace.o [5]
.text ro code 0x800'5232 0x14 tolower.o [5]
.rodata const 0x800'5248 0x888 eg91.o [2]
.rodata const 0x800'5ad0 0x1f0 lte_comms.o [2]
.rodata const 0x800'5cc0 0x50 iar_Stoulx.o [5]
.text ro code 0x800'5d10 0x44 putchar.o [5]
.text ro code 0x800'5d54 0x38 zero_init3.o [7]
.text ro code 0x800'5d8c 0x34 stm32wbaxx_it.o [2]
.text ro code 0x800'5dc0 0x10 stm32wbaxx_hal.o [4]
.text ro code 0x800'5dd0 0x14 stm32wbaxx_hal_hsem.o [4]
.text ro code 0x800'5de4 0x2 stm32wbaxx_hal_hsem.o [4]
.rodata const 0x800'5de8 0x30 lte_comms.o [2]
.rodata const 0x800'5e18 0x2c eg91.o [2]
.text ro code 0x800'5e44 0x28 data_init.o [7]
.rodata const 0x800'5e6c 0x24 gpio.o [2]
.rodata const 0x800'5e90 0x24 gpio.o [2]
.text ro code 0x800'5eb4 0x22 fpinit_M.o [6]
.iar.init_table const 0x800'5ed8 0x20 - Linker created -
.text ro code 0x800'5ef8 0x1e cmain.o [7]
.text ro code 0x800'5f16 0x4 low_level_init.o [5]
.text ro code 0x800'5f1a 0x4 exit.o [5]
.text ro code 0x800'5f20 0xa cexit.o [7]
.text ro code 0x800'5f2c 0x1c cstartup_M.o [7]
.text ro code 0x800'5f48 0x16 xprout.o [5]
.text ro code 0x800'5f60 0x10 startup_stm32wba52xx.o [3]
.rodata const 0x800'5f70 0x8 system_stm32wbaxx.o [1]
.text ro code 0x800'5f78 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f7c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f80 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f84 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f88 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f8c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f90 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f94 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f98 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5f9c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fa0 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fa4 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fa8 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fac 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fb0 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fb4 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fb8 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fbc 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fc0 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fc4 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fc8 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fcc 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fd0 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fd4 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fd8 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fdc 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fe0 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fe4 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fe8 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5fec 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5ff0 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5ff4 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5ff8 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'5ffc 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6000 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6004 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6008 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'600c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6010 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6014 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6018 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'601c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6020 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6024 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6028 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'602c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6030 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6034 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6038 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'603c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6040 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6044 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6048 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'604c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6050 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6054 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6058 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'605c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6060 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6064 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6068 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'606c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6070 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6074 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6078 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'607c 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6080 0x4 startup_stm32wba52xx.o [3]
.text ro code 0x800'6084 0x4 startup_stm32wba52xx.o [3]
.rodata const 0x800'6088 0x0 zero_init3.o [7]
.rodata const 0x800'6088 0x0 lz77_init_single.o [7]
Initializer bytes const 0x800'6088 0x54 <for P2-1>
- 0x800'60dc 0x5f80
"P2", part 1 of 3: 0xd8
P2-1 0x2000'0000 0xd8 <Init block>
.data inited 0x2000'0000 0xc stm32wbaxx_hal.o [4]
.data inited 0x2000'000c 0x4 system_stm32wbaxx.o [1]
.data inited 0x2000'0010 0x38 xlocale_c.o [5]
.data inited 0x2000'0048 0x48 xlocale_c.o [5]
.data inited 0x2000'0090 0x48 xfiles.o [5]
- 0x2000'00d8 0xd8
"P2", part 2 of 3: 0xa00
.bss zero 0x2000'00d8 0x5e0 usart.o [2]
.bss zero 0x2000'06b8 0x270 lte_comms.o [2]
.bss zero 0x2000'0928 0x94 usart.o [2]
.bss zero 0x2000'09bc 0x94 usart.o [2]
.bss zero 0x2000'0a50 0x50 xfiles.o [5]
.bss zero 0x2000'0aa0 0x30 rtc.o [2]
.bss zero 0x2000'0ad0 0x4 strtok.o [5]
.bss zero 0x2000'0ad4 0x4 xfail_s.o [5]
- 0x2000'0ad8 0xa00
"P2", part 3 of 3: 0x400
CSTACK 0x2000'0ad8 0x400 <Block>
CSTACK uninit 0x2000'0ad8 0x400 <Block tail>
- 0x2000'0ed8 0x400
Unused ranges:
From To Size
---- -- ----
0x800'60dc 0x80f'ffff 0xf'9f24
0x2000'0ed8 0x2000'ffff 0xf128
*******************************************************************************
*** INIT TABLE
***
Address Size
------- ----
Zero (__iar_zero_init3)
1 destination range, total size 0xa00:
0x2000'00d8 0xa00
Copy/lz77 (__iar_lz77_init_single3)
1 source range, total size 0x54 (38% of destination):
0x800'6088 0x54
1 destination range, total size 0xd8:
0x2000'0000 0xd8
*******************************************************************************
*** MODULE SUMMARY
***
Module ro code ro data rw data
------ ------- ------- -------
command line/config:
---------------------------------------------------
Total:
C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\CMSIS_6603591812247902717.dir: [1]
system_stm32wbaxx.o 260 10 4
---------------------------------------------------
Total: 260 10 4
C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir: [2]
eg91.o 1'856 2'228
gpio.o 324 72
icache.o 30
lte_comms.o 956 544 624
main.o 204
rtc.o 188 48
stm32wbaxx_hal_msp.o 64
stm32wbaxx_it.o 52
usart.o 848 1'800
---------------------------------------------------
Total: 4'522 2'844 2'472
C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\EWARM_18443280873093131863.dir: [3]
startup_stm32wba52xx.o 636
---------------------------------------------------
Total: 636
C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir: [4]
stm32wbaxx_hal.o 268 4 12
stm32wbaxx_hal_cortex.o 296
stm32wbaxx_hal_dma.o 190
stm32wbaxx_hal_gpio.o 612
stm32wbaxx_hal_hsem.o 22
stm32wbaxx_hal_icache.o 56
stm32wbaxx_hal_pwr_ex.o 92
stm32wbaxx_hal_rcc.o 1'888
stm32wbaxx_hal_rcc_ex.o 520
stm32wbaxx_hal_rtc.o 380
stm32wbaxx_hal_rtc_ex.o 196
stm32wbaxx_hal_uart.o 3'734
stm32wbaxx_hal_uart_ex.o 252
---------------------------------------------------
Total: 8'506 4 12
dl7M_tlf.a: [5]
abort.o 6
exit.o 4
iar_Stoulx.o 338 80
isspace.o 20
low_level_init.o 4
printf.o 40
putchar.o 68
strcspn.o 34
strspn.o 34
strstr.o 44
strtok.o 76 4
tolower.o 20
xfail_s.o 64 4
xfiles.o 28 152
xlocale_c.o 60 55 128
xprintffull_nomb.o 3'786
xprout.o 22
---------------------------------------------------
Total: 4'620 163 288
m7M_tls.a: [6]
DblAddSub.o 590
DblCmpGe.o 52
DblCmpLe.o 52
DblDiv.o 582
DblMul.o 426
DblToS32.o 54
DblToU32.o 34
S32ToDbl.o 34
U32ToDbl.o 28
fpinit_M.o 34
frexp.o 112
ldexp.o 314
---------------------------------------------------
Total: 2'312
rt7M_tl.a: [7]
ABImemclr4.o 6
ABImemcpy_small.o 24
ABImemset48.o 50
ABImemset_small.o 18
I64DivMod_small.o 262
I64DivZer.o 2
cexit.o 10
cmain.o 30
cstartup_M.o 28
data_init.o 40
lz77_init_single.o 126
memchr.o 88
memset.o 20
strchr.o 22
strlen_small.o 20
strncpy_small.o 30
zero_init3.o 56
---------------------------------------------------
Total: 832
shb_l.a: [8]
exit.o 20
---------------------------------------------------
Total: 20
Gaps 29 6
Linker created 32 1'024
-------------------------------------------------------
Grand Total: 21'737 3'059 3'800
*******************************************************************************
*** ENTRY LIST
***
Entry Address Size Type Object
----- ------- ---- ---- ------
.iar.init_table$$Base 0x800'5ed8 -- Gb - Linker created -
.iar.init_table$$Limit 0x800'5ef8 -- Gb - Linker created -
?main 0x800'5ef9 Code Gb cmain.o [7]
ADC4_IRQHandler 0x800'6075 Code Wk startup_stm32wba52xx.o [3]
AES_IRQHandler 0x800'6059 Code Wk startup_stm32wba52xx.o [3]
AHBPrescTable 0x800'45a0 0x8 Data Gb system_stm32wbaxx.o [1]
APBPrescTable 0x800'5f70 0x8 Data Gb system_stm32wbaxx.o [1]
AT_ExecuteCommand 0x800'4a21 0x48 Code Lc eg91.o [2]
AT_RetrieveData 0x800'4909 0x118 Code Lc eg91.o [2]
BusFault_Handler 0x800'5d93 0x2 Code Gb stm32wbaxx_it.o [2]
CSTACK$$Base 0x2000'0ad8 -- Gb - Linker created -
CSTACK$$Limit 0x2000'0ed8 -- Gb - Linker created -
DebugMon_Handler 0x800'5d99 0x2 Code Gb stm32wbaxx_it.o [2]
EG91_AutomaticPlmnSelection
0x800'4d87 0x10 Code Gb eg91.o [2]
EG91_GetPsNetworkRegistrationStatus
0x800'4dc5 0x3e Code Gb eg91.o [2]
EG91_GetSignalQualityStatus
0x800'4d1d 0x2e Code Gb eg91.o [2]
EG91_GetUARTConfig 0x800'4e2d 0x82 Code Gb eg91.o [2]
EG91_Init 0x800'4ab1 0x254 Code Gb eg91.o [2]
EG91_PSAttach 0x800'4d4b 0x34 Code Gb eg91.o [2]
EG91_RegisterBusIO 0x800'4a69 0x3a Code Gb eg91.o [2]
EG91_RegisterTickCb 0x800'4ebb 0x12 Code Gb eg91.o [2]
EG91_ResetToFactoryDefault
0x800'4e21 0xc Code Gb eg91.o [2]
EXTI0_IRQHandler 0x800'5fa9 Code Wk startup_stm32wba52xx.o [3]
EXTI10_IRQHandler 0x800'5fd1 Code Wk startup_stm32wba52xx.o [3]
EXTI11_IRQHandler 0x800'5fd5 Code Wk startup_stm32wba52xx.o [3]
EXTI12_IRQHandler 0x800'5fd9 Code Wk startup_stm32wba52xx.o [3]
EXTI13_IRQHandler 0x800'5fdd Code Wk startup_stm32wba52xx.o [3]
EXTI14_IRQHandler 0x800'5fe1 Code Wk startup_stm32wba52xx.o [3]
EXTI15_IRQHandler 0x800'5fe5 Code Wk startup_stm32wba52xx.o [3]
EXTI1_IRQHandler 0x800'5fad Code Wk startup_stm32wba52xx.o [3]
EXTI2_IRQHandler 0x800'5fb1 Code Wk startup_stm32wba52xx.o [3]
EXTI3_IRQHandler 0x800'5fb5 Code Wk startup_stm32wba52xx.o [3]
EXTI4_IRQHandler 0x800'5fb9 Code Wk startup_stm32wba52xx.o [3]
EXTI5_IRQHandler 0x800'5fbd Code Wk startup_stm32wba52xx.o [3]
EXTI6_IRQHandler 0x800'5fc1 Code Wk startup_stm32wba52xx.o [3]
EXTI7_IRQHandler 0x800'5fc5 Code Wk startup_stm32wba52xx.o [3]
EXTI8_IRQHandler 0x800'5fc9 Code Wk startup_stm32wba52xx.o [3]
EXTI9_IRQHandler 0x800'5fcd Code Wk startup_stm32wba52xx.o [3]
Eg91Obj 0x2000'06b8 0x270 Data Gb lte_comms.o [2]
Error_Handler 0x800'36a1 0x4 Code Gb main.o [2]
FLASH_IRQHandler 0x800'5f95 Code Wk startup_stm32wba52xx.o [3]
FLASH_S_IRQHandler 0x800'5f99 Code Wk startup_stm32wba52xx.o [3]
FPU_IRQHandler 0x800'6061 Code Wk startup_stm32wba52xx.o [3]
GPDMA1_Channel0_IRQHandler
0x800'5ff1 Code Wk startup_stm32wba52xx.o [3]
GPDMA1_Channel1_IRQHandler
0x800'5ff5 Code Wk startup_stm32wba52xx.o [3]
GPDMA1_Channel2_IRQHandler
0x800'5ff9 Code Wk startup_stm32wba52xx.o [3]
GPDMA1_Channel3_IRQHandler
0x800'5ffd Code Wk startup_stm32wba52xx.o [3]
GPDMA1_Channel4_IRQHandler
0x800'6001 Code Wk startup_stm32wba52xx.o [3]
GPDMA1_Channel5_IRQHandler
0x800'6005 Code Wk startup_stm32wba52xx.o [3]
GPDMA1_Channel6_IRQHandler
0x800'6009 Code Wk startup_stm32wba52xx.o [3]
GPDMA1_Channel7_IRQHandler
0x800'600d Code Wk startup_stm32wba52xx.o [3]
GTZC_IRQHandler 0x800'5f9d Code Wk startup_stm32wba52xx.o [3]
HAL_DMA_Abort 0x800'2dc1 0x7c Code Gb stm32wbaxx_hal_dma.o [4]
HAL_DMA_Abort_IT 0x800'2e3d 0x2a Code Gb stm32wbaxx_hal_dma.o [4]
HAL_Delay 0x800'45e9 0x28 Code Wk stm32wbaxx_hal.o [4]
HAL_GPIO_DeInit 0x800'3c53 0xca Code Gb stm32wbaxx_hal_gpio.o [4]
HAL_GPIO_Init 0x800'3ae5 0x16e Code Gb stm32wbaxx_hal_gpio.o [4]
HAL_GPIO_TogglePin 0x800'3d27 0x10 Code Gb stm32wbaxx_hal_gpio.o [4]
HAL_GPIO_WritePin 0x800'3d1d 0xa Code Gb stm32wbaxx_hal_gpio.o [4]
HAL_GetTick 0x800'2db5 0xc Code Wk stm32wbaxx_hal.o [4]
HAL_HSEM_FreeCallback 0x800'5de5 0x2 Code Wk stm32wbaxx_hal_hsem.o [4]
HAL_HSEM_IRQHandler 0x800'5dd1 0x10 Code Gb stm32wbaxx_hal_hsem.o [4]
HAL_ICACHE_ConfigAssociativityMode
0x800'4865 0x18 Code Gb stm32wbaxx_hal_icache.o [4]
HAL_ICACHE_Enable 0x800'487d 0xe Code Gb stm32wbaxx_hal_icache.o [4]
HAL_IncTick 0x800'5dc1 0x10 Code Wk stm32wbaxx_hal.o [4]
HAL_Init 0x800'3ddd 0x30 Code Gb stm32wbaxx_hal.o [4]
HAL_InitTick 0x800'3d49 0x94 Code Wk stm32wbaxx_hal.o [4]
HAL_MspInit 0x800'45a9 0x40 Code Gb stm32wbaxx_hal_msp.o [2]
HAL_NVIC_DisableIRQ 0x800'3a3b 0x1e Code Gb stm32wbaxx_hal_cortex.o [4]
HAL_NVIC_EnableIRQ 0x800'3a25 0x16 Code Gb stm32wbaxx_hal_cortex.o [4]
HAL_NVIC_SetPriority 0x800'39d7 0x4e Code Gb stm32wbaxx_hal_cortex.o [4]
HAL_NVIC_SetPriorityGrouping
0x800'39bd 0x1a Code Gb stm32wbaxx_hal_cortex.o [4]
HAL_PWREx_ControlVoltageScaling
0x800'4415 0x4e Code Gb stm32wbaxx_hal_pwr_ex.o [4]
HAL_RCCEx_PeriphCLKConfig
0x800'37b5 0x1f8 Code Gb stm32wbaxx_hal_rcc_ex.o [4]
HAL_RCC_ClockConfig 0x800'3333 0x15c Code Gb stm32wbaxx_hal_rcc.o [4]
HAL_RCC_GetHCLKFreq 0x800'34b3 0x1a Code Gb stm32wbaxx_hal_rcc.o [4]
HAL_RCC_GetPCLK1Freq 0x800'34cd 0xa Code Gb stm32wbaxx_hal_rcc.o [4]
HAL_RCC_GetPCLK2Freq 0x800'34d7 0x12 Code Gb stm32wbaxx_hal_rcc.o [4]
HAL_RCC_GetPCLK7Freq 0x800'34e9 0x8 Code Gb stm32wbaxx_hal_rcc.o [4]
HAL_RCC_GetPLL1RFreq 0x800'3511 0x10 Code Gb stm32wbaxx_hal_rcc.o [4]
HAL_RCC_GetSysClockFreq
0x800'348f 0x24 Code Gb stm32wbaxx_hal_rcc.o [4]
HAL_RCC_OscConfig 0x800'2e89 0x478 Code Gb stm32wbaxx_hal_rcc.o [4]
HAL_RTCEx_PrivilegeModeSet
0x800'4827 0x30 Code Gb stm32wbaxx_hal_rtc_ex.o [4]
HAL_RTCEx_SetWakeUpTimer
0x800'47a1 0x7a Code Gb stm32wbaxx_hal_rtc_ex.o [4]
HAL_RTC_Init 0x800'4625 0xa0 Code Gb stm32wbaxx_hal_rtc.o [4]
HAL_RTC_MspInit 0x800'3fbd 0x48 Code Gb rtc.o [2]
HAL_RTC_WaitForSynchro 0x800'46cb 0x36 Code Gb stm32wbaxx_hal_rtc.o [4]
HAL_SYSTICK_CLKSourceConfig
0x800'3a7d 0x48 Code Gb stm32wbaxx_hal_cortex.o [4]
HAL_SYSTICK_Config 0x800'3a59 0x24 Code Gb stm32wbaxx_hal_cortex.o [4]
HAL_UARTEx_DisableFifoMode
0x800'36b5 0x3c Code Gb stm32wbaxx_hal_uart_ex.o [4]
HAL_UARTEx_RxEventCallback
0x800'2e81 0x2 Code Wk stm32wbaxx_hal_uart.o [4]
HAL_UARTEx_RxFifoFullCallback
0x800'2e87 0x2 Code Wk stm32wbaxx_hal_uart_ex.o [4]
HAL_UARTEx_SetRxFifoThreshold
0x800'3707 0x14 Code Gb stm32wbaxx_hal_uart_ex.o [4]
HAL_UARTEx_SetTxFifoThreshold
0x800'36f1 0x16 Code Gb stm32wbaxx_hal_uart_ex.o [4]
HAL_UARTEx_TxFifoEmptyCallback
0x800'2e85 0x2 Code Wk stm32wbaxx_hal_uart_ex.o [4]
HAL_UART_DeInit 0x800'1c5d 0x3e Code Gb stm32wbaxx_hal_uart.o [4]
HAL_UART_ErrorCallback 0x800'2e7f 0x2 Code Wk stm32wbaxx_hal_uart.o [4]
HAL_UART_IRQHandler 0x800'1da1 0x29e Code Gb stm32wbaxx_hal_uart.o [4]
HAL_UART_Init 0x800'1bd5 0x34 Code Gb stm32wbaxx_hal_uart.o [4]
HAL_UART_MspDeInit 0x800'2c43 0x5a Code Gb usart.o [2]
HAL_UART_MspInit 0x800'2b21 0xca Code Gb usart.o [2]
HAL_UART_Receive_IT 0x800'1d47 0x26 Code Gb stm32wbaxx_hal_uart.o [4]
HAL_UART_RxCpltCallback
0x800'2d35 0x20 Code Gb usart.o [2]
HAL_UART_Transmit 0x800'1ca7 0x9a Code Gb stm32wbaxx_hal_uart.o [4]
HAL_UART_TxCpltCallback
0x800'2e83 0x2 Code Wk stm32wbaxx_hal_uart.o [4]
HASH_IRQHandler 0x800'6065 Code Wk startup_stm32wba52xx.o [3]
HSEM_IRQHandler 0x800'5dbd 0x4 Code Gb stm32wbaxx_it.o [2]
HSEM_S_IRQHandler 0x800'6081 Code Wk startup_stm32wba52xx.o [3]
HardFault_Handler 0x800'5d8f 0x2 Code Gb stm32wbaxx_it.o [2]
I2C1_ER_IRQHandler 0x800'602d Code Wk startup_stm32wba52xx.o [3]
I2C1_EV_IRQHandler 0x800'6029 Code Wk startup_stm32wba52xx.o [3]
I2C3_ER_IRQHandler 0x800'6051 Code Wk startup_stm32wba52xx.o [3]
I2C3_EV_IRQHandler 0x800'604d Code Wk startup_stm32wba52xx.o [3]
ICACHE_IRQHandler 0x800'6071 Code Wk startup_stm32wba52xx.o [3]
IWDG_IRQHandler 0x800'5fe9 Code Wk startup_stm32wba52xx.o [3]
LEDStatus_Active 0x800'3e7b 0x4 Code Gb gpio.o [2]
LEDStatus_Inactive 0x800'3e7f 0x2 Code Gb gpio.o [2]
LPTIM1_IRQHandler 0x800'603d Code Wk startup_stm32wba52xx.o [3]
LPTIM2_IRQHandler 0x800'6041 Code Wk startup_stm32wba52xx.o [3]
LPUART1_IRQHandler 0x800'6039 Code Wk startup_stm32wba52xx.o [3]
LTE_GetIMEI 0x800'42fb 0x8 Code Gb lte_comms.o [2]
LTE_GetModuleFirmwareRevision
0x800'42dd 0x8 Code Gb lte_comms.o [2]
LTE_GetModuleID 0x800'42e5 0x6 Code Gb lte_comms.o [2]
LTE_GetSignalQualityStatus
0x800'42b5 0x16 Code Gb lte_comms.o [2]
LTE_GetSimId 0x800'42f3 0x8 Code Gb lte_comms.o [2]
LTE_HardwarePowerDown 0x800'3efb 0x3e Code Gb gpio.o [2]
LTE_HardwarePowerUp 0x800'3e89 0x68 Code Gb gpio.o [2]
LTE_Init 0x800'418d 0x120 Code Gb lte_comms.o [2]
LTE_UART_FlushBuffer 0x800'2cd5 0x18 Code Gb usart.o [2]
LTE_UART_ReceiveSingleData
0x800'2d05 0x30 Code Gb usart.o [2]
LTE_UART_SendData 0x800'2ced 0x18 Code Gb usart.o [2]
LTE_UART_SetBaudrate 0x800'2c9d 0x2c Code Gb usart.o [2]
MX_GPIO_Init 0x800'3e11 0x6a Code Gb gpio.o [2]
MX_ICACHE_Init 0x800'4011 0x1e Code Gb icache.o [2]
MX_LPUART1_UART_Init 0x800'2a65 0x50 Code Gb usart.o [2]
MX_RTC_Init 0x800'3f55 0x68 Code Gb rtc.o [2]
MX_USART1_UART_Init 0x800'2ab5 0x54 Code Gb usart.o [2]
MemManage_Handler 0x800'5d91 0x2 Code Gb stm32wbaxx_it.o [2]
NMI_Handler 0x800'5d8d 0x2 Code Gb stm32wbaxx_it.o [2]
Network_Init 0x800'4031 0x154 Code Gb lte_comms.o [2]
PKA_IRQHandler 0x800'6069 Code Wk startup_stm32wba52xx.o [3]
PVD_IRQHandler 0x800'5f81 Code Wk startup_stm32wba52xx.o [3]
ParseNumber 0x800'48bd 0x38 Code Lc eg91.o [2]
PendSV_Handler 0x800'5d9b 0x2 Code Gb stm32wbaxx_it.o [2]
RADIO_IRQHandler 0x800'6079 Code Wk startup_stm32wba52xx.o [3]
RAMCFG_IRQHandler 0x800'5f91 Code Wk startup_stm32wba52xx.o [3]
RCC_IRQHandler 0x800'5fa1 Code Wk startup_stm32wba52xx.o [3]
RCC_PLL1_GetVCOOutputFreq
0x800'3521 0x78 Code Lc stm32wbaxx_hal_rcc.o [4]
RCC_S_IRQHandler 0x800'5fa5 Code Wk startup_stm32wba52xx.o [3]
RNG_IRQHandler 0x800'605d Code Wk startup_stm32wba52xx.o [3]
RTC_EnterInitMode 0x800'4701 0x48 Code Gb stm32wbaxx_hal_rtc.o [4]
RTC_ExitInitMode 0x800'4749 0x4c Code Gb stm32wbaxx_hal_rtc.o [4]
RTC_IRQHandler 0x800'5f85 Code Wk startup_stm32wba52xx.o [3]
RTC_S_IRQHandler 0x800'5f89 Code Wk startup_stm32wba52xx.o [3]
Region$$Table$$Base 0x800'5ed8 -- Gb - Linker created -
Region$$Table$$Limit 0x800'5ef8 -- Gb - Linker created -
Reset_Handler 0x800'5f61 Code Wk startup_stm32wba52xx.o [3]
ReturnKeywords 0x800'5248 0x888 Data Gb eg91.o [2]
SAES_IRQHandler 0x800'5fed Code Wk startup_stm32wba52xx.o [3]
SPI1_IRQHandler 0x800'6031 Code Wk startup_stm32wba52xx.o [3]
SPI3_IRQHandler 0x800'606d Code Wk startup_stm32wba52xx.o [3]
SVC_Handler 0x800'5d97 0x2 Code Gb stm32wbaxx_it.o [2]
SecureFault_Handler 0x800'5f79 Code Wk startup_stm32wba52xx.o [3]
SysTick_Handler 0x800'5d9d 0x4 Code Gb stm32wbaxx_it.o [2]
SystemClock_Config 0x800'3619 0x88 Code Gb main.o [2]
SystemCoreClock 0x2000'000c 0x4 Data Gb system_stm32wbaxx.o [1]
SystemCoreClockUpdate 0x800'44b9 0xc6 Code Gb system_stm32wbaxx.o [1]
SystemInit 0x800'44a5 0x12 Code Gb system_stm32wbaxx.o [1]
TAMP_IRQHandler 0x800'5f8d Code Wk startup_stm32wba52xx.o [3]
TIM16_IRQHandler 0x800'6045 Code Wk startup_stm32wba52xx.o [3]
TIM17_IRQHandler 0x800'6049 Code Wk startup_stm32wba52xx.o [3]
TIM1_BRK_IRQHandler 0x800'6011 Code Wk startup_stm32wba52xx.o [3]
TIM1_CC_IRQHandler 0x800'601d Code Wk startup_stm32wba52xx.o [3]
TIM1_TRG_COM_IRQHandler
0x800'6019 Code Wk startup_stm32wba52xx.o [3]
TIM1_UP_IRQHandler 0x800'6015 Code Wk startup_stm32wba52xx.o [3]
TIM2_IRQHandler 0x800'6021 Code Wk startup_stm32wba52xx.o [3]
TIM3_IRQHandler 0x800'6025 Code Wk startup_stm32wba52xx.o [3]
TSC_IRQHandler 0x800'6055 Code Wk startup_stm32wba52xx.o [3]
TimeLeftFromExpiration 0x800'48f5 0x14 Code Lc eg91.o [2]
UARTEx_SetNbDataToProcess
0x800'375d 0x3e Code Lc stm32wbaxx_hal_uart_ex.o [4]
UARTEx_SetNbDataToProcess::denominator
0x800'37a4 0x8 Data Lc stm32wbaxx_hal_uart_ex.o [4]
UARTEx_SetNbDataToProcess::numerator
0x800'379c 0x8 Data Lc stm32wbaxx_hal_uart_ex.o [4]
UARTPrescTable 0x800'2660 0x18 Data Gb stm32wbaxx_hal_uart.o [4]
UART_AdvFeatureConfig 0x800'22db 0xc6 Code Gb stm32wbaxx_hal_uart.o [4]
UART_CheckIdleState 0x800'23a1 0x8e Code Gb stm32wbaxx_hal_uart.o [4]
UART_DMAAbortOnError 0x800'2655 0xc Code Lc stm32wbaxx_hal_uart.o [4]
UART_EndRxTransfer 0x800'25cb 0x22 Code Lc stm32wbaxx_hal_uart.o [4]
UART_RxData 0x2000'00d8 0x5e0 Data Gb usart.o [2]
UART_RxISR_16BIT 0x800'26c9 0x50 Code Lc stm32wbaxx_hal_uart.o [4]
UART_RxISR_16BIT_FIFOEN
0x800'2899 0xa0 Code Lc stm32wbaxx_hal_uart.o [4]
UART_RxISR_8BIT 0x800'2679 0x50 Code Lc stm32wbaxx_hal_uart.o [4]
UART_RxISR_8BIT_FIFOEN 0x800'27c5 0xa0 Code Lc stm32wbaxx_hal_uart.o [4]
UART_SetConfig 0x800'20b1 0x218 Code Gb stm32wbaxx_hal_uart.o [4]
UART_Start_Receive_IT 0x800'24bf 0xf2 Code Gb stm32wbaxx_hal_uart.o [4]
UART_WaitOnFlagUntilTimeout
0x800'242f 0x90 Code Gb stm32wbaxx_hal_uart.o [4]
USART1_IRQHandler 0x800'5da1 0x14 Code Gb stm32wbaxx_it.o [2]
USART2_IRQHandler 0x800'6035 Code Wk startup_stm32wba52xx.o [3]
UsageFault_Handler 0x800'5d95 0x2 Code Gb stm32wbaxx_it.o [2]
WKUP_IRQHandler 0x800'607d Code Wk startup_stm32wba52xx.o [3]
WKUP_S_IRQHandler 0x800'6085 Code Wk startup_stm32wba52xx.o [3]
WWDG_IRQHandler 0x800'5f7d Code Wk startup_stm32wba52xx.o [3]
_LC 0x800'015d 0x6 Code Lc xprintffull_nomb.o [5]
_LitobFullNoMb 0x800'0e45 0x114 Code Lc xprintffull_nomb.o [5]
_LocaleC_isspace 0x800'1a81 0x14 Code Gb xlocale_c.o [5]
_LocaleC_isupper 0x800'1a75 0x2 Code Gb xlocale_c.o [5]
_LocaleC_tolower 0x800'1a95 0xc Code Gb xlocale_c.o [5]
_Locale_lconv 0x2000'0010 0x38 Data Lc xlocale_c.o [5]
_PrintfFullNoMb 0x800'0163 0xcb2 Code Gb xprintffull_nomb.o [5]
_Prout 0x800'5f49 0x16 Code Gb xprout.o [5]
_PutcharsFullNoMb 0x800'0fb1 0x2e Code Lc xprintffull_nomb.o [5]
_Strtok_ssave 0x2000'0ad0 0x4 Data Lc strtok.o [5]
__Vectors 0x800'0000 -- Gb startup_stm32wba52xx.o [3]
__Vectors_End 0x800'015c Data Gb startup_stm32wba52xx.o [3]
__Vectors_Size {Abs} 0x15c -- Gb startup_stm32wba52xx.o [3]
__aeabi_cdcmple 0x800'11f1 Code Gb DblCmpLe.o [6]
__aeabi_cdrcmple 0x800'1225 Code Gb DblCmpGe.o [6]
__aeabi_d2iz 0x800'1395 Code Gb DblToS32.o [6]
__aeabi_d2uiz 0x800'1889 Code Gb DblToU32.o [6]
__aeabi_ddiv 0x800'1641 Code Gb DblDiv.o [6]
__aeabi_dmul 0x800'18c9 Code Gb DblMul.o [6]
__aeabi_dsub 0x800'155d Code Gb DblAddSub.o [6]
__aeabi_i2d 0x800'13cd Code Gb S32ToDbl.o [6]
__aeabi_ldiv0 0x800'1bbd Code Gb I64DivZer.o [7]
__aeabi_memclr4 0x800'37ad Code Gb ABImemclr4.o [7]
__aeabi_ui2d 0x800'18ad Code Gb U32ToDbl.o [6]
__cmain 0x800'5ef9 Code Gb cmain.o [7]
__exit 0x800'1bc1 0x14 Code Gb exit.o [8]
__iar_Fail_s 0x800'10bd 0x1c Code Gb xfail_s.o [5]
__iar_Memchr 0x800'1111 Code Gb memchr.o [7]
__iar_Memset4_word 0x800'4471 Code Gb ABImemset48.o [7]
__iar_Memset8_word 0x800'4471 Code Gb ABImemset48.o [7]
__iar_Stdout 0x2000'0090 0x48 Data Gb xfiles.o [5]
__iar_Stoul 0x800'51cb 0x2 Code Gb iar_Stoulx.o [5]
__iar_Stoulx 0x800'5089 0x13c Code Gb iar_Stoulx.o [5]
__iar_Strchr 0x800'10a5 Code Gb strchr.o [7]
__iar_data_init3 0x800'5e45 0x28 Code Gb data_init.o [7]
__iar_frexp 0x800'118d Code Gb frexp.o [6]
__iar_frexpl 0x800'118d Code Gb frexp.o [6]
__iar_globLocale 0x2000'0048 0x48 Data Lc xlocale_c.o [5]
__iar_global_Locale 0x800'1aa1 0x4 Code Gb xlocale_c.o [5]
__iar_init_vfp 0x800'5eb5 Code Gb fpinit_M.o [6]
__iar_ldexp64 0x800'1259 Code Gb ldexp.o [6]
__iar_lz77_init_single3
0x800'1027 0x7e Code Gb lz77_init_single.o [7]
__iar_program_start 0x800'5f2d Code Gb cstartup_M.o [7]
__iar_scalbln64 0x800'1259 Code Gb ldexp.o [6]
__iar_scalbn64 0x800'1259 Code Gb ldexp.o [6]
__iar_small_Memcpy 0x800'116d Code Gb ABImemcpy_small.o [7]
__iar_small_Memset 0x800'4ffd Code Gb ABImemset_small.o [7]
__iar_small_Memset_word
0x800'4ffd Code Gb ABImemset_small.o [7]
__iar_small_memcpy 0x800'1169 Code Gb ABImemcpy_small.o [7]
__iar_small_memcpy4 0x800'1169 Code Gb ABImemcpy_small.o [7]
__iar_small_memcpy8 0x800'1169 Code Gb ABImemcpy_small.o [7]
__iar_small_memset 0x800'4ffd Code Gb ABImemset_small.o [7]
__iar_small_strlen 0x800'10fd Code Gb strlen_small.o [7]
__iar_small_strncpy 0x800'489d Code Gb strncpy_small.o [7]
__iar_small_uldivmod 0x800'1ab1 Code Gb I64DivMod_small.o [7]
__iar_softfp___iar_frexp64
0x800'1181 Code Gb frexp.o [6]
__iar_softfp_frexp 0x800'1181 Code Gb frexp.o [6]
__iar_softfp_frexpl 0x800'1181 Code Gb frexp.o [6]
__iar_zero_init3 0x800'5d55 0x38 Code Gb zero_init3.o [7]
__low_level_init 0x800'5f17 0x4 Code Gb low_level_init.o [5]
__vector_table 0x800'0000 Data Gb startup_stm32wba52xx.o [3]
__write 0x800'2d5d 0x32 Code Gb usart.o [2]
_call_main 0x800'5f05 Code Gb cmain.o [7]
_exit 0x800'5f21 Code Gb cexit.o [7]
abort 0x800'1bb7 0x6 Code Gb abort.o [5]
atoi 0x800'51cd 0x2 Code Gb iar_Stoulx.o [5]
digits 0x800'5ce8 0x28 Data Lc iar_Stoulx.o [5]
exit 0x800'5f1b 0x4 Code Gb exit.o [5]
hlpuart1 0x2000'0928 0x94 Data Gb usart.o [2]
hrtc 0x2000'0aa0 0x30 Data Gb rtc.o [2]
huart1 0x2000'09bc 0x94 Data Gb usart.o [2]
isspace 0x800'521f 0x14 Code Gb isspace.o [5]
ldexp 0x800'1259 Code Gb ldexp.o [6]
ldexpl 0x800'1259 Code Gb ldexp.o [6]
localeconv 0x800'1aa5 0x4 Code Gb xlocale_c.o [5]
main 0x800'35e9 0x30 Code Gb main.o [2]
memchr 0x800'1111 Code Gb memchr.o [7]
memset 0x800'4611 0x14 Code Gb memset.o [7]
ndigs 0x800'5cc0 0x28 Data Lc iar_Stoulx.o [5]
obuf 0x2000'0a50 0x50 Data Lc xfiles.o [5]
printf 0x800'43ed 0x28 Code Gb printf.o [5]
putchar 0x800'5d11 0x44 Code Gb putchar.o [5]
scalbln 0x800'1259 Code Gb ldexp.o [6]
scalblnl 0x800'1259 Code Gb ldexp.o [6]
scalbn 0x800'1259 Code Gb ldexp.o [6]
scalbnl 0x800'1259 Code Gb ldexp.o [6]
scale 0x800'0f59 0x46 Code Lc xprintffull_nomb.o [5]
sec_hand 0x2000'0ad4 0x4 Data Lc xfail_s.o [5]
strchr 0x800'10a5 Code Gb strchr.o [7]
strcspn 0x800'51fd 0x22 Code Gb strcspn.o [5]
strspn 0x800'51db 0x22 Code Gb strspn.o [5]
strstr 0x800'500f 0x2c Code Gb strstr.o [5]
strtok 0x800'503d 0x4c Code Gb strtok.o [5]
tolower 0x800'5233 0x14 Code Gb tolower.o [5]
uwTick 0x2000'0004 0x4 Data Gb stm32wbaxx_hal.o [4]
uwTickFreq 0x2000'0000 0x1 Data Gb stm32wbaxx_hal.o [4]
uwTickPrio 0x2000'0008 0x4 Data Gb stm32wbaxx_hal.o [4]
[1] = C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\CMSIS_6603591812247902717.dir
[2] = C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\Core_13247989168731456611.dir
[3] = C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\EWARM_18443280873093131863.dir
[4] = C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Obj\STM32WBAxx_HAL_Driver_814230103969653557.dir
[5] = dl7M_tlf.a
[6] = m7M_tls.a
[7] = rt7M_tl.a
[8] = shb_l.a
21'737 bytes of readonly code memory
3'059 bytes of readonly data memory
3'800 bytes of readwrite data memory
Errors: none
Warnings: none

517
EWARM/settings/Project.wsdt Normal file

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@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<userBookmarks />

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@ -0,0 +1,40 @@
@REM This batch file has been generated by the IAR Embedded Workbench
@REM C-SPY Debugger, as an aid to preparing a command line for running
@REM the cspybat command line utility using the appropriate settings.
@REM
@REM Note that this file is generated every time a new debug session
@REM is initialized, so you may want to move or rename the file before
@REM making changes.
@REM
@REM You can launch cspybat by typing the name of this batch file followed
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
@REM
@REM Read about available command line parameters in the C-SPY Debugging
@REM Guide. Hints about additional command line parameters that may be
@REM useful in specific cases:
@REM --download_only Downloads a code image without starting a debug
@REM session afterwards.
@REM --silent Omits the sign-on message.
@REM --timeout Limits the maximum allowed execution time.
@REM
@echo off
if not "%~1" == "" goto debugFile
@echo on
"C:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\settings\WiseEye-LTE.WiseEye-LTE.general.xcl" --backend -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\settings\WiseEye-LTE.WiseEye-LTE.driver.xcl"
@echo off
goto end
:debugFile
@echo on
"C:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\settings\WiseEye-LTE.WiseEye-LTE.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\settings\WiseEye-LTE.WiseEye-LTE.driver.xcl"
@echo off
:end

View File

@ -0,0 +1,31 @@
param([String]$debugfile = "");
# This powershell file has been generated by the IAR Embedded Workbench
# C - SPY Debugger, as an aid to preparing a command line for running
# the cspybat command line utility using the appropriate settings.
#
# Note that this file is generated every time a new debug session
# is initialized, so you may want to move or rename the file before
# making changes.
#
# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
# by the name of the debug file (usually an ELF / DWARF or UBROF file).
#
# Read about available command line parameters in the C - SPY Debugging
# Guide. Hints about additional command line parameters that may be
# useful in specific cases :
# --download_only Downloads a code image without starting a debug
# session afterwards.
# --silent Omits the sign - on message.
# --timeout Limits the maximum allowed execution time.
#
if ($debugfile -eq "")
{
& "C:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\settings\WiseEye-LTE.WiseEye-LTE.general.xcl" --backend -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\settings\WiseEye-LTE.WiseEye-LTE.driver.xcl"
}
else
{
& "C:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\settings\WiseEye-LTE.WiseEye-LTE.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\settings\WiseEye-LTE.WiseEye-LTE.driver.xcl"
}

View File

@ -0,0 +1,31 @@
"--endian=little"
"--cpu=Cortex-M33.no_se"
"--fpu=VFPv5_SP"
"-p"
"C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\ST\STM32WBA52CG.ddf"
"--drv_verify_download"
"--semihosting"
"--device=STM32WBA52CG"
"--drv_interface=SWD"
"--stlink_reset_strategy=0,2"
"--drv_swo_clock_setup=64000000,0,2000000"
"--drv_catch_exceptions=0x000"
"--drv_debug_ap=1"
"--stlink_probe_supplied_power=3.3"

View File

@ -0,0 +1,17 @@
"C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armPROC.dll"
"C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armSTLINK.dll"
"C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\Exe\WiseEye-LTE.out"
--plugin="C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armbat.dll"
--device_macro="C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32WBAxx.dmac"
--device_macro="C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/debugger/ST/STM32WBAxx_DBG.dmac"
--flash_loader="C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm/config/flashloader/ST/FlashSTM32WBAxxxG.board"

View File

@ -0,0 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<crun>
<version>1</version>
<filter_entries>
<filter index="0" type="default">
<type>*</type>
<start_file>*</start_file>
<end_file>*</end_file>
<action_debugger>0</action_debugger>
<action_log>1</action_log>
</filter>
</filter_entries>
</crun>

View File

@ -0,0 +1,4 @@
<?xml version="1.0" encoding="UTF-8"?>
<Project>
<WindowStorage />
</Project>

View File

@ -0,0 +1,124 @@
<?xml version="1.0"?>
<settings>
<Stack>
<FillEnabled>0</FillEnabled>
<OverflowWarningsEnabled>1</OverflowWarningsEnabled>
<WarningThreshold>90</WarningThreshold>
<SpWarningsEnabled>1</SpWarningsEnabled>
<WarnLogOnly>1</WarnLogOnly>
<UseTrigger>1</UseTrigger>
<TriggerName>main</TriggerName>
<LimitSize>0</LimitSize>
<ByteLimit>50</ByteLimit>
</Stack>
<PlDriver>
<FirstRun>0</FirstRun>
<MemConfigValue>C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\ST\STM32WBA52CG.ddf</MemConfigValue>
</PlDriver>
<ArmDriver>
<EnableCache>0</EnableCache>
<EnforceMemoryConfiguration>1</EnforceMemoryConfiguration>
</ArmDriver>
<StLinkDriver>
<stlinkserialNo>0670FF343636574D43054237</stlinkserialNo>
<stlinkfoundProbes />
<LeaveTargetRunning>_ 0</LeaveTargetRunning>
<CStepIntDis>_ 0</CStepIntDis>
<stlinkResetStyle>0</stlinkResetStyle>
<stlinkResetStrategy>2</stlinkResetStrategy>
</StLinkDriver>
<Trace1>
<Enabled>0</Enabled>
<ShowSource>1</ShowSource>
</Trace1>
<TerminalIO>
<InputSource>1</InputSource>
<InputMode>10</InputMode>
<Filename>$PROJ_DIR$\TermIOInput.txt</Filename>
<InputEcho>1</InputEcho>
<ShowReset>0</ShowReset>
<InputEncoding>2</InputEncoding>
<OutputEncoding>2</OutputEncoding>
</TerminalIO>
<Exceptions>
<StopOnUncaught>_ 0</StopOnUncaught>
<StopOnThrow>_ 0</StopOnThrow>
</Exceptions>
<SWOTraceHWSettings>
<OverrideDefaultClocks>0</OverrideDefaultClocks>
<CpuClock>64000000</CpuClock>
<ClockAutoDetect>0</ClockAutoDetect>
<ClockWanted>2000000</ClockWanted>
<JtagSpeed>2000000</JtagSpeed>
<Prescaler>32</Prescaler>
<TimeStampPrescIndex>0</TimeStampPrescIndex>
<TimeStampPrescData>0</TimeStampPrescData>
<PcSampCYCTAP>1</PcSampCYCTAP>
<PcSampPOSTCNT>15</PcSampPOSTCNT>
<PcSampIndex>0</PcSampIndex>
<DataLogMode>0</DataLogMode>
<ITMportsEnable>0</ITMportsEnable>
<ITMportsTermIO>0</ITMportsTermIO>
<ITMportsLogFile>0</ITMportsLogFile>
<ITMlogFile>$PROJ_DIR$\ITM.log</ITMlogFile>
</SWOTraceHWSettings>
<Trace2>
<Enabled>0</Enabled>
<ShowSource>0</ShowSource>
</Trace2>
<SWOTraceWindow>
<PcSampling>0</PcSampling>
<InterruptLogs>0</InterruptLogs>
<ForcedTimeStamps>0</ForcedTimeStamps>
<EventCPI>0</EventCPI>
<EventEXC>0</EventEXC>
<EventFOLD>0</EventFOLD>
<EventLSU>0</EventLSU>
<EventSLEEP>0</EventSLEEP>
</SWOTraceWindow>
<DataLog>
<GraphEnabled>0</GraphEnabled>
<LogEnabled>0</LogEnabled>
<ShowTimeLog>1</ShowTimeLog>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
</DataLog>
<InterruptLog>
<GraphEnabled>0</GraphEnabled>
<LogEnabled>0</LogEnabled>
<ShowTimeLog>1</ShowTimeLog>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
<SumSortOrder>0</SumSortOrder>
</InterruptLog>
<EventLog>
<GraphEnabled>0</GraphEnabled>
<LogEnabled>0</LogEnabled>
<ShowTimeLog>1</ShowTimeLog>
<Title_0>Ch3</Title_0>
<Symbol_0>0 0 1</Symbol_0>
<Title_1>Ch2</Title_1>
<Symbol_1>0 0 1</Symbol_1>
<Title_2>Ch1</Title_2>
<Symbol_2>0 0 1</Symbol_2>
<Title_3>Ch0</Title_3>
<Symbol_3>0 0 1</Symbol_3>
<SumEnabled>0</SumEnabled>
<ShowTimeSum>1</ShowTimeSum>
<SumSortOrder>0</SumSortOrder>
</EventLog>
<DisassembleMode>
<mode>0</mode>
</DisassembleMode>
<Breakpoints2>
<Count>0</Count>
</Breakpoints2>
<TermIOLog>
<LoggingEnabled>_ 0</LoggingEnabled>
<LogFile>_ ""</LogFile>
</TermIOLog>
<Aliases>
<Count>0</Count>
<SuppressDialog>0</SuppressDialog>
</Aliases>
</settings>

View File

@ -0,0 +1,506 @@
<?xml version="1.0" encoding="UTF-8"?>
<Workspace>
<ConfigDictionary>
<CurrentConfigs>
<Project>WiseEye-LTE/WiseEye-LTE</Project>
</CurrentConfigs>
</ConfigDictionary>
<WindowStorage>
<ChildIdMap>
<TB_CMSISPACK>34048</TB_CMSISPACK>
<TB_MAIN2>34049</TB_MAIN2>
<WIN_BREAKPOINTS>34050</WIN_BREAKPOINTS>
<WIN_BUILD>34051</WIN_BUILD>
<WIN_CALL_GRAPH>34052</WIN_CALL_GRAPH>
<WIN_CUSTOM_SFR>34053</WIN_CUSTOM_SFR>
<WIN_C_STAT>34054</WIN_C_STAT>
<WIN_DEBUG_LOG>34055</WIN_DEBUG_LOG>
<WIN_FIND_ALL_DECLARATIONS>34056</WIN_FIND_ALL_DECLARATIONS>
<WIN_FIND_ALL_REFERENCES>34057</WIN_FIND_ALL_REFERENCES>
<WIN_FIND_IN_FILES>34058</WIN_FIND_IN_FILES>
<WIN_SELECT_AMBIGUOUS_DEFINITIONS>34059</WIN_SELECT_AMBIGUOUS_DEFINITIONS>
<WIN_SOURCEBROWSE_LOG>34060</WIN_SOURCEBROWSE_LOG>
<WIN_SOURCE_BROWSE2>34061</WIN_SOURCE_BROWSE2>
<WIN_TOOL_OUTPUT>34062</WIN_TOOL_OUTPUT>
<WIN_WORKSPACE>34063</WIN_WORKSPACE>
</ChildIdMap>
<Desktop>
<IarPane-34048>
<ToolBarCmdIds>
<item>34001</item>
<item>0</item>
</ToolBarCmdIds>
</IarPane-34048>
<IarPane-34049>
<ToolBarCmdIds>
<item>57600</item>
<item>57601</item>
<item>57603</item>
<item>33024</item>
<item>0</item>
<item>57607</item>
<item>0</item>
<item>57635</item>
<item>57634</item>
<item>57637</item>
<item>0</item>
<item>57643</item>
<item>57644</item>
<item>0</item>
<item>33090</item>
<item>33057</item>
<item>57636</item>
<item>57640</item>
<item>57641</item>
<item>33026</item>
<item>33065</item>
<item>33063</item>
<item>33064</item>
<item>33053</item>
<item>33054</item>
<item>0</item>
<item>33035</item>
<item>33036</item>
<item>34399</item>
<item>0</item>
<item>33038</item>
<item>33039</item>
<item>33877</item>
<item>0</item>
</ToolBarCmdIds>
</IarPane-34049>
<IarPane-34055>
<col-names>
<item>Log</item>
<item>_I0</item>
</col-names>
<col-widths>
<item>249</item>
<item>20</item>
</col-widths>
<DebugLogLevel>2</DebugLogLevel>
<LiveFile>$PROJ_DIR$\DebugLog.log</LiveFile>
<LiveLogEnabled>0</LiveLogEnabled>
<LiveFilterLevel>0</LiveFilterLevel>
</IarPane-34055>
<IarPane-34063>
<NodeDict>
<ExpandedNode>WiseEye-LTE</ExpandedNode>
<ExpandedNode>WiseEye-LTE/Application</ExpandedNode>
<ExpandedNode>WiseEye-LTE/Application/User</ExpandedNode>
<ExpandedNode>WiseEye-LTE/Application/User/Core</ExpandedNode>
</NodeDict>
</IarPane-34063>
<ControlBarVersion>
<Major>14</Major>
<Minor>44</Minor>
</ControlBarVersion>
<MFCToolBarParameters>
<Tooltips>1</Tooltips>
<ShortcutKeys>1</ShortcutKeys>
<LargeIcons>0</LargeIcons>
<MenuAnimation>0</MenuAnimation>
<RecentlyUsedMenus>1</RecentlyUsedMenus>
<MenuShadows>1</MenuShadows>
<ShowAllMenusAfterDelay>1</ShowAllMenusAfterDelay>
<CommandsUsage>160000000400598400000100000048810000010000005584000006000000108400000F000000</CommandsUsage>
</MFCToolBarParameters>
<CommandManager>
<CommandsWithoutImages>0A007784000007840000FFFFFFFF86840000808C000044D5000055840000568400005984000048810000</CommandsWithoutImages>
<MenuUserImages>1300048400004D000000318400005400000020810000910100000F810000890100000C81000086010000068400004F000000038400004C0000000E8400005100000030840000530000001F810000900100000E810000880100000B81000085010000D184000076010000058400004E000000028400004B000000108400005200000032840000550000000A840000500000000D81000087010000</MenuUserImages>
</CommandManager>
<Pane-59393>
<ID>0</ID>
<RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat>
<RectRecentDocked>000000002C030000A00500003D030000</RectRecentDocked>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-59393>
<BasePane-59393>
<IsVisible>1</IsVisible>
</BasePane-59393>
<Pane-34050>
<ID>34050</ID>
<RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
<RectRecentDocked>000000000000000022010000B1000000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34050>
<BasePane-34050>
<IsVisible>0</IsVisible>
</BasePane-34050>
<IarPane-34050 />
<Pane--1>
<ID>4294967295</ID>
<RectRecentFloat>8604000049000000A005000043030000</RectRecentFloat>
<RectRecentDocked>8604000032000000A00500002C030000</RectRecentDocked>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane--1>
<BasePane--1>
<IsVisible>1</IsVisible>
</BasePane--1>
<Pane-34051>
<ID>34051</ID>
<RectRecentFloat>D8040000B3010000FA05000064020000</RectRecentFloat>
<RectRecentDocked>8A0400004A0000009C05000012030000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34051>
<BasePane-34051>
<IsVisible>1</IsVisible>
</BasePane-34051>
<IarPane-34051>
<col-names>
<item>File</item>
<item>Line</item>
<item>Messages</item>
<item>_I0</item>
</col-names>
<col-widths>
<item>65</item>
<item>40</item>
<item>143</item>
<item>20</item>
</col-widths>
<BuildLogLevel>2</BuildLogLevel>
<LiveFile>$WS_DIR$\BuildLog.log</LiveFile>
<LiveLogEnabled>0</LiveLogEnabled>
<LiveFilterLevel>0</LiveFilterLevel>
</IarPane-34051>
<Pane-34055>
<ID>34055</ID>
<RectRecentFloat>D8040000B3010000FA05000064020000</RectRecentFloat>
<RectRecentDocked>8A0400004A0000009C05000012030000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34055>
<BasePane-34055>
<IsVisible>1</IsVisible>
</BasePane-34055>
<Pane-34056>
<ID>34056</ID>
<RectRecentFloat>D8040000B3010000FA05000064020000</RectRecentFloat>
<RectRecentDocked>8A0400004A0000009C05000012030000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34056>
<BasePane-34056>
<IsVisible>0</IsVisible>
</BasePane-34056>
<IarPane-34056>
<ColumnWidth0>93</ColumnWidth0>
<ColumnWidth1>13</ColumnWidth1>
<ColumnWidth2>159</ColumnWidth2>
<FilterLevel>2</FilterLevel>
<LiveFile></LiveFile>
<LiveLogEnabled>0</LiveLogEnabled>
<LiveFilterLevel>-1</LiveFilterLevel>
</IarPane-34056>
<Pane-34057>
<ID>34057</ID>
<RectRecentFloat>D8040000B3010000FA05000064020000</RectRecentFloat>
<RectRecentDocked>8A0400004A0000009C05000012030000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34057>
<BasePane-34057>
<IsVisible>0</IsVisible>
</BasePane-34057>
<IarPane-34057>
<ColumnWidth0>93</ColumnWidth0>
<ColumnWidth1>13</ColumnWidth1>
<ColumnWidth2>159</ColumnWidth2>
<FilterLevel>2</FilterLevel>
<LiveFile></LiveFile>
<LiveLogEnabled>0</LiveLogEnabled>
<LiveFilterLevel>-1</LiveFilterLevel>
</IarPane-34057>
<Pane-34058>
<ID>34058</ID>
<RectRecentFloat>D8040000B3010000FA05000064020000</RectRecentFloat>
<RectRecentDocked>8A0400004A0000009C05000012030000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34058>
<BasePane-34058>
<IsVisible>0</IsVisible>
</BasePane-34058>
<IarPane-34058 />
<Pane-34059>
<ID>34059</ID>
<RectRecentFloat>D8040000B3010000FA05000064020000</RectRecentFloat>
<RectRecentDocked>8A0400004A0000009C05000012030000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34059>
<BasePane-34059>
<IsVisible>0</IsVisible>
</BasePane-34059>
<IarPane-34059>
<ColumnWidth0>93</ColumnWidth0>
<ColumnWidth1>13</ColumnWidth1>
<ColumnWidth2>159</ColumnWidth2>
<FilterLevel>2</FilterLevel>
<LiveFile></LiveFile>
<LiveLogEnabled>0</LiveLogEnabled>
<LiveFilterLevel>-1</LiveFilterLevel>
</IarPane-34059>
<Pane-34060>
<ID>34060</ID>
<RectRecentFloat>D8040000B3010000FA05000064020000</RectRecentFloat>
<RectRecentDocked>8A0400004A0000009C05000012030000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34060>
<BasePane-34060>
<IsVisible>1</IsVisible>
</BasePane-34060>
<IarPane-34060>
<FilterLevel>2</FilterLevel>
<LiveFile>$WS_DIR/SourceBrowseLog.log</LiveFile>
<LiveLogEnabled>0</LiveLogEnabled>
<LiveFilterLevel>-1</LiveFilterLevel>
</IarPane-34060>
<Pane-34062>
<ID>34062</ID>
<RectRecentFloat>D8040000B3010000FA05000064020000</RectRecentFloat>
<RectRecentDocked>8A0400004A0000009C05000012030000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34062>
<BasePane-34062>
<IsVisible>0</IsVisible>
</BasePane-34062>
<IarPane-34062>
<FilterLevel>2</FilterLevel>
<LiveFile></LiveFile>
<LiveLogEnabled>0</LiveLogEnabled>
<LiveFilterLevel>-1</LiveFilterLevel>
</IarPane-34062>
<Pane-34052>
<ID>34052</ID>
<RectRecentFloat>000000001700000080020000A8000000</RectRecentFloat>
<RectRecentDocked>00000000000000008002000091000000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34052>
<BasePane-34052>
<IsVisible>0</IsVisible>
</BasePane-34052>
<IarPane-34052>
<cg_type>
<item>2</item>
</cg_type>
<cg_symbol>
<item></item>
</cg_symbol>
<cg_user>
<item></item>
</cg_user>
<cg_display>
<item>&lt;Right-click on a symbol in the editor to show a call graph&gt;</item>
</cg_display>
<cg_def_file>
<item></item>
</cg_def_file>
<cg_def_line>
<item>0</item>
</cg_def_line>
<cg_def_col>
<item>0</item>
</cg_def_col>
<cg_call_file>
<item></item>
</cg_call_file>
<cg_call_line>
<item>0</item>
</cg_call_line>
<cg_call_col>
<item>0</item>
</cg_call_col>
<col-names>
<item>File</item>
<item>Function</item>
<item>Line</item>
</col-names>
<col-widths>
<item>200</item>
<item>700</item>
<item>100</item>
</col-widths>
</IarPane-34052>
<Pane-34053>
<ID>34053</ID>
<RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
<RectRecentDocked>000000000000000022010000B1000000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34053>
<BasePane-34053>
<IsVisible>0</IsVisible>
</BasePane-34053>
<IarPane-34053 />
<Pane-34054>
<ID>34054</ID>
<RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
<RectRecentDocked>000000000000000022010000B1000000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34054>
<BasePane-34054>
<IsVisible>0</IsVisible>
</BasePane-34054>
<IarPane-34054>
<kCStatFilterHistoryKey />
<col-names>
<item>Check</item>
<item>File</item>
<item>Line</item>
<item>Message</item>
<item>Severity</item>
</col-names>
<col-widths>
<item>200</item>
<item>200</item>
<item>100</item>
<item>500</item>
<item>100</item>
</col-widths>
</IarPane-34054>
<Pane-34061>
<ID>34061</ID>
<RectRecentFloat>000000001700000080020000A8000000</RectRecentFloat>
<RectRecentDocked>00000000000000008002000091000000</RectRecentDocked>
<RecentFrameAlignment>32768</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34061>
<BasePane-34061>
<IsVisible>0</IsVisible>
</BasePane-34061>
<IarPane-34061>
<SB_FileFilter>
<item>2</item>
</SB_FileFilter>
<SB_TypeFilter>
<item>0</item>
</SB_TypeFilter>
<SB_SBW_File>
<item>C:\Users\Admin\Documents\.Projects\7. Cellular Relay Controller\LTE-Code\WiseEye-LTE\EWARM\WiseEye-LTE\BrowseInfo\WiseEye-LTE.pbw</item>
</SB_SBW_File>
<col-names>
<item>File</item>
<item>Name</item>
<item>Scope</item>
<item>Symbol type</item>
</col-names>
<col-widths>
<item>300</item>
<item>300</item>
<item>300</item>
<item>300</item>
</col-widths>
</IarPane-34061>
<Pane-34063>
<ID>34063</ID>
<RectRecentFloat>00000000170000000601000078010000</RectRecentFloat>
<RectRecentDocked>0000000032000000F50000002C030000</RectRecentDocked>
<RecentFrameAlignment>4096</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>32767</MRUWidth>
<PinState>0</PinState>
</Pane-34063>
<BasePane-34063>
<IsVisible>1</IsVisible>
</BasePane-34063>
<DockingManager-256>
<DockingPaneAndPaneDividers>000000000E000000000000000010000001000000FFFFFFFFFFFFFFFFF500000032000000F90000002C03000001000000020000100400000001000000D0FEFFFFD00300000F85000000000000000000000000000000000000010000000F850000010000000F850000000000000080000000000000FFFFFFFFFFFFFFFF000000000000000004000000040000000000000001000000040000000100000000000000000000000D85000000000000000000000000000000000000010000000D850000010000000D850000000000000080000000000000FFFFFFFFFFFFFFFF00000000000000000400000004000000000000000100000004000000010000000000000000000000068500000000000000000000000000000000000001000000068500000100000006850000000000000080000000000000FFFFFFFFFFFFFFFF00000000000000000400000004000000000000000100000004000000010000000000000000000000058500000000000000000000000000000000000001000000058500000100000005850000000000000080000000000000FFFFFFFFFFFFFFFF00000000000000000400000004000000000000000100000004000000010000000000000000000000048500000000000000000000000000000000000001000000048500000100000004850000000000000080000000000000FFFFFFFFFFFFFFFF00000000000000000400000004000000000000000100000004000000010000000000000000000000028500000000000000000000000000000000000001000000028500000100000002850000000000000040000001000000FFFFFFFFFFFFFFFF8204000032000000860400002C03000001000000020000100400000001000000000000000000000000000000000000000000000001000000FFFFFFFF08000000038500000785000008850000098500000A8500000B8500000C8500000E850000FFFF02000B004354616262656450616E6500400000010000008604000049000000A0050000430300008604000032000000A00500002C030000000000004080005608000000FFFEFF054200750069006C006400010000000385000001000000FFFFFFFFFFFFFFFFFFFEFF094400650062007500670020004C006F006700010000000785000001000000FFFFFFFFFFFFFFFFFFFEFF0C4400650063006C00610072006100740069006F006E007300000000000885000001000000FFFFFFFFFFFFFFFFFFFEFF0A5200650066006500720065006E00630065007300000000000985000001000000FFFFFFFFFFFFFFFFFFFEFF0D460069006E006400200069006E002000460069006C0065007300000000000A85000001000000FFFFFFFFFFFFFFFFFFFEFF1541006D0062006900670075006F0075007300200044006500660069006E006900740069006F006E007300000000000B85000001000000FFFFFFFFFFFFFFFFFFFEFF1153006F0075007200630065002000420072006F0077007300650020004C006F006700010000000C85000001000000FFFFFFFFFFFFFFFFFFFEFF0B54006F006F006C0020004F0075007400700075007400000000000E85000001000000FFFFFFFFFFFFFFFF0600000000000000000000000000000000000000000000000000000001000000FFFFFFFF0385000001000000FFFFFFFF03850000000000000000000000000000</DockingPaneAndPaneDividers>
</DockingManager-256>
<MFCToolBar-34048>
<Name>CMSIS-Pack</Name>
<Buttons>00200000010000000100FFFF01001100434D4643546F6F6C426172427574746F6ED184000002000000AF010000FFFEFF00000000000000000000000000010000000100000000000000FFFEFF0A43004D005300490053002D005000610063006B0018000000</Buttons>
</MFCToolBar-34048>
<Pane-34048>
<ID>34048</ID>
<RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat>
<RectRecentDocked>CB03000000000000F90300001A000000</RectRecentDocked>
<RecentFrameAlignment>8192</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>24</MRUWidth>
<PinState>0</PinState>
</Pane-34048>
<BasePane-34048>
<IsVisible>1</IsVisible>
</BasePane-34048>
<MFCToolBar-34049>
<Name>Main</Name>
<Buttons>00200000010000002100FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000D9010000FFFEFF000000000000000000000000000100000001000000018001E1000000000000DA010000FFFEFF000000000000000000000000000100000001000000018003E1000000000400DC010000FFFEFF00000000000000000000000000010000000100000001800081000000000000B9010000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000018007E1000000000400DF010000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000018023E1000000000400E1010000FFFEFF000000000000000000000000000100000001000000018022E1000000000400E0010000FFFEFF000000000000000000000000000100000001000000018025E1000000000400E2010000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001802BE1000000000400E3010000FFFEFF00000000000000000000000000010000000100000001802CE1000000000400E4010000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000FFFF01000D005061737465436F6D626F426F784281000000000400FFFFFFFFFFFEFF000100000000000000010000000000000001000000B400000002002050FFFFFFFFFFFEFF009600000000000000000001802181000000000400CB010000FFFEFF000000000000000000000000000100000001000000018024E1000000000400D4010000FFFEFF000000000000000000000000000100000001000000018028E1000000000400D3010000FFFEFF000000000000000000000000000100000001000000018029E1000000000400D5010000FFFEFF00000000000000000000000000010000000100000001800281000000000400BA010000FFFEFF00000000000000000000000000010000000100000001802981000000000400CF010000FFFEFF00000000000000000000000000010000000100000001802781000000000400CD010000FFFEFF00000000000000000000000000010000000100000001802881000000000400CE010000FFFEFF00000000000000000000000000010000000100000001801D81000000000000C7010000FFFEFF00000000000000000000000000010000000100000001801E81000000000400C8010000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001800B81000002000400BE010000FFFEFF00000000000000000000000000010000000100000001800C81000002000000BF010000FFFEFF00000000000000000000000000010000000100000001805F86000002000000D2010000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001800E81000002000000C1010000FFFEFF00000000000000000000000000010000000100000001800F81000002000000C2010000FFFEFF00000000000000000000000000010000000100000001805584000002000000FFFFFFFFFFFEFF1B44006F0077006E006C006F0061006400200061006300740069007600650020006100700070006C00690063006100740069006F006E00000000000000000001000000000000000100000000000000FFFEFF044D00610069006E00E4010000</Buttons>
</MFCToolBar-34049>
<Pane-34049>
<ID>34049</ID>
<RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat>
<RectRecentDocked>0000000000000000CB0300001A000000</RectRecentDocked>
<RecentFrameAlignment>8192</RecentFrameAlignment>
<RecentRowIndex>0</RecentRowIndex>
<IsFloating>0</IsFloating>
<MRUWidth>484</MRUWidth>
<PinState>0</PinState>
</Pane-34049>
<BasePane-34049>
<IsVisible>1</IsVisible>
</BasePane-34049>
</Desktop>
<MDIWindows>
<MDIClientArea-0>
<MDITabsState>01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000001000000030000000200000001000000FFFEFF1B2400570053005F0044004900520024005C002E002E005C0043006F00720065005C005300720063005C006700700069006F002E00630001000000FFFF010017004966436F6E74656E7453746F726167654D6663496D706CFFFEFF00FFFEFFFF26013C003F0078006D006C002000760065007200730069006F006E003D00220031002E0030002200200065006E0063006F00640069006E0067003D0022005500540046002D00380022003F003E000A003C0052006F006F0074003E000A0020002000200020003C004E0075006D0052006F00770073003E0031003C002F004E0075006D0052006F00770073003E000A0020002000200020003C004E0075006D0043006F006C0073003E0031003C002F004E0075006D0043006F006C0073003E000A0020002000200020003C00580050006F0073003E0030003C002F00580050006F0073003E000A0020002000200020003C00590050006F0073003E0030003C002F00590050006F0073003E000A0020002000200020003C00530065006C00530074006100720074003E0030003C002F00530065006C00530074006100720074003E000A0020002000200020003C00530065006C0045006E0064003E0030003C002F00530065006C0045006E0064003E000A0020002000200020003C00580050006F00730032003E0030003C002F00580050006F00730032003E000A0020002000200020003C00590050006F00730032003E0038003C002F00590050006F00730032003E000A0020002000200020003C00530065006C005300740061007200740032003E0031003000370034003C002F00530065006C005300740061007200740032003E000A0020002000200020003C00530065006C0045006E00640032003E0031003000370034003C002F00530065006C0045006E00640032003E000A003C002F0052006F006F0074003E000A00FFFEFF066700700069006F002E00630000000000FFFFFFFFFFFFFFFFFFFEFF1B2400570053005F0044004900520024005C002E002E005C0043006F00720065005C005300720063005C006D00610069006E002E006300010000000180FFFEFF00FFFEFFFF21013C003F0078006D006C002000760065007200730069006F006E003D00220031002E0030002200200065006E0063006F00640069006E0067003D0022005500540046002D00380022003F003E000A003C0052006F006F0074003E000A0020002000200020003C004E0075006D0052006F00770073003E0031003C002F004E0075006D0052006F00770073003E000A0020002000200020003C004E0075006D0043006F006C0073003E0031003C002F004E0075006D0043006F006C0073003E000A0020002000200020003C00580050006F0073003E0030003C002F00580050006F0073003E000A0020002000200020003C00590050006F0073003E0030003C002F00590050006F0073003E000A0020002000200020003C00530065006C00530074006100720074003E0030003C002F00530065006C00530074006100720074003E000A0020002000200020003C00530065006C0045006E0064003E0030003C002F00530065006C0045006E0064003E000A0020002000200020003C00580050006F00730032003E0030003C002F00580050006F00730032003E000A0020002000200020003C00590050006F00730032003E00370033003C002F00590050006F00730032003E000A0020002000200020003C00530065006C005300740061007200740032003E0030003C002F00530065006C005300740061007200740032003E000A0020002000200020003C00530065006C0045006E00640032003E0030003C002F00530065006C0045006E00640032003E000A003C002F0052006F006F0074003E000A00FFFEFF066D00610069006E002E00630000000000FFFFFFFFFFFFFFFFFFFEFF1C2400570053005F0044004900520024005C002E002E005C0043006F00720065005C005300720063005C00750073006100720074002E006300010000000180FFFEFF00FFFEFFFF28013C003F0078006D006C002000760065007200730069006F006E003D00220031002E0030002200200065006E0063006F00640069006E0067003D0022005500540046002D00380022003F003E000A003C0052006F006F0074003E000A0020002000200020003C004E0075006D0052006F00770073003E0031003C002F004E0075006D0052006F00770073003E000A0020002000200020003C004E0075006D0043006F006C0073003E0031003C002F004E0075006D0043006F006C0073003E000A0020002000200020003C00580050006F0073003E0030003C002F00580050006F0073003E000A0020002000200020003C00590050006F0073003E0030003C002F00590050006F0073003E000A0020002000200020003C00530065006C00530074006100720074003E0030003C002F00530065006C00530074006100720074003E000A0020002000200020003C00530065006C0045006E0064003E0030003C002F00530065006C0045006E0064003E000A0020002000200020003C00580050006F00730032003E0030003C002F00580050006F00730032003E000A0020002000200020003C00590050006F00730032003E003200330035003C002F00590050006F00730032003E000A0020002000200020003C00530065006C005300740061007200740032003E0037003700320039003C002F00530065006C005300740061007200740032003E000A0020002000200020003C00530065006C0045006E00640032003E0037003700320039003C002F00530065006C0045006E00640032003E000A003C002F0052006F006F0074003E000A00FFFEFF07750073006100720074002E00630000000000FFFFFFFFFFFFFFFF0000000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000100000002000000F9000000490000008204000043030000</MDITabsState>
</MDIClientArea-0>
</MDIWindows>
</WindowStorage>
</Workspace>

View File

@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<userBookmarks />

View File

@ -0,0 +1,562 @@
;********************************************************************************
;* File Name : startup_stm32wba52xx.s
;* Author : MCD Application Team
;* Description : STM32WBA5xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M33 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2022 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD SecureFault_Handler ; Secure Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection Interrupt
DCD RTC_IRQHandler ; RTC non-secure interrupt
DCD RTC_S_IRQHandler ; RTC secure interrupt
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
DCD RAMCFG_IRQHandler ; RAMCFG global
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
DCD RCC_IRQHandler ; RCC non-secure global interrupt
DCD RCC_S_IRQHandler ; RCC secure global interrupt
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
DCD IWDG_IRQHandler ; IWDG global interrupt
DCD SAES_IRQHandler ; Secure AES global interrupt
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
DCD TIM2_IRQHandler ; TIM2 global interrupt
DCD TIM3_IRQHandler ; TIM3 global interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
DCD SPI1_IRQHandler ; SPI1 global interrupt
DCD USART1_IRQHandler ; USART1 global interrupt
DCD USART2_IRQHandler ; USART2 global interrupt
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
DCD TIM16_IRQHandler ; TIM16 global interrupt
DCD TIM17_IRQHandler ; TIM17 global interrupt
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; I2C3 event interrupt
DCD I2C3_ER_IRQHandler ; I2C3 error interrupt
DCD 0 ; Reserved
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD AES_IRQHandler ; AES global interrupt
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU global interrupt
DCD HASH_IRQHandler ; HASH global interrupt
DCD PKA_IRQHandler ; PKA global interrupt
DCD SPI3_IRQHandler ; SPI3 global interrupt
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
DCD ADC4_IRQHandler ; LP ADC (12bits) global interrupt
DCD RADIO_IRQHandler ; 2.4GHz RADIO global interrupt
DCD WKUP_IRQHandler ; PWR global WKUP pin interrupt
DCD HSEM_IRQHandler ; HSEM non-secure global interrupt
DCD HSEM_S_IRQHandler ; HSEM secure global interrupt
DCD WKUP_S_IRQHandler ; PWR secure global WKUP pin interrupt
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SecureFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SecureFault_Handler
B SecureFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK RTC_S_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_S_IRQHandler
B RTC_S_IRQHandler
PUBWEAK TAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_IRQHandler
B TAMP_IRQHandler
PUBWEAK RAMCFG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RAMCFG_IRQHandler
B RAMCFG_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK FLASH_S_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_S_IRQHandler
B FLASH_S_IRQHandler
PUBWEAK GTZC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GTZC_IRQHandler
B GTZC_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK RCC_S_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_S_IRQHandler
B RCC_S_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK EXTI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI5_IRQHandler
B EXTI5_IRQHandler
PUBWEAK EXTI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI6_IRQHandler
B EXTI6_IRQHandler
PUBWEAK EXTI7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI7_IRQHandler
B EXTI7_IRQHandler
PUBWEAK EXTI8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI8_IRQHandler
B EXTI8_IRQHandler
PUBWEAK EXTI9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_IRQHandler
B EXTI9_IRQHandler
PUBWEAK EXTI10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI10_IRQHandler
B EXTI10_IRQHandler
PUBWEAK EXTI11_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI11_IRQHandler
B EXTI11_IRQHandler
PUBWEAK EXTI12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI12_IRQHandler
B EXTI12_IRQHandler
PUBWEAK EXTI13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI13_IRQHandler
B EXTI13_IRQHandler
PUBWEAK EXTI14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI14_IRQHandler
B EXTI14_IRQHandler
PUBWEAK EXTI15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_IRQHandler
B EXTI15_IRQHandler
PUBWEAK IWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IWDG_IRQHandler
B IWDG_IRQHandler
PUBWEAK SAES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAES_IRQHandler
B SAES_IRQHandler
PUBWEAK GPDMA1_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPDMA1_Channel0_IRQHandler
B GPDMA1_Channel0_IRQHandler
PUBWEAK GPDMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPDMA1_Channel1_IRQHandler
B GPDMA1_Channel1_IRQHandler
PUBWEAK GPDMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPDMA1_Channel2_IRQHandler
B GPDMA1_Channel2_IRQHandler
PUBWEAK GPDMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPDMA1_Channel3_IRQHandler
B GPDMA1_Channel3_IRQHandler
PUBWEAK GPDMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPDMA1_Channel4_IRQHandler
B GPDMA1_Channel4_IRQHandler
PUBWEAK GPDMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPDMA1_Channel5_IRQHandler
B GPDMA1_Channel5_IRQHandler
PUBWEAK GPDMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPDMA1_Channel6_IRQHandler
B GPDMA1_Channel6_IRQHandler
PUBWEAK GPDMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPDMA1_Channel7_IRQHandler
B GPDMA1_Channel7_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK TSC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TSC_IRQHandler
B TSC_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK HASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HASH_IRQHandler
B HASH_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK ICACHE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ICACHE_IRQHandler
B ICACHE_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK RADIO_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RADIO_IRQHandler
B RADIO_IRQHandler
PUBWEAK WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WKUP_IRQHandler
B WKUP_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK HSEM_S_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_S_IRQHandler
B HSEM_S_IRQHandler
PUBWEAK WKUP_S_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WKUP_S_IRQHandler
B WKUP_S_IRQHandler
END

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
define symbol __region_SRAM2_start__ = 0x20010000;
define symbol __region_SRAM2_end__ = 0x2001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM2_region { };

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x20007FFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20008000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
define symbol __region_SRAM2_start__ = 0x20010000;
define symbol __region_SRAM2_end__ = 0x2001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM2_region { };

194
WiseEye-LTE-2.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
CAD.formats=
CAD.pinconfig=
CAD.provider=
CORTEX_M33_NS.userName=CORTEX_M33
File.Version=6
GPIO.groupedBy=
KeepUserPlacement=false
LPUART1.BaudRate=115200
LPUART1.IPParameters=BaudRate
MMTAppRegionsCount=0
MMTConfigApplied=false
Mcu.CPN=STM32WBA52CGU6
Mcu.ContextProject=TrustZoneDisabled
Mcu.Family=STM32WBA
Mcu.IP0=CORTEX_M33_NS
Mcu.IP1=ICACHE
Mcu.IP2=LPUART1
Mcu.IP3=MEMORYMAP
Mcu.IP4=NVIC
Mcu.IP5=PWR
Mcu.IP6=RCC
Mcu.IP7=SYS
Mcu.IP8=USART1
Mcu.IPNb=9
Mcu.Name=STM32WBA52CGUx
Mcu.Package=UFQFPN48
Mcu.Pin0=PB12
Mcu.Pin1=PB11
Mcu.Pin10=OSC_IN
Mcu.Pin11=PA10
Mcu.Pin12=VP_CORTEX_M33_NS_VS_Hclk
Mcu.Pin13=VP_ICACHE_VS_ICACHE
Mcu.Pin14=VP_PWR_VS_SECSignals
Mcu.Pin15=VP_SYS_VS_Systick
Mcu.Pin16=VP_MEMORYMAP_VS_MEMORYMAP
Mcu.Pin2=PA8
Mcu.Pin3=PC15-OSC32_OUT
Mcu.Pin4=PC14-OSC32_IN
Mcu.Pin5=PB7
Mcu.Pin6=PB4 (NJTRST)
Mcu.Pin7=PA15 (JTDI)
Mcu.Pin8=PB0
Mcu.Pin9=OSC_OUT
Mcu.PinsNb=17
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32WBA52CGUx
MxCube.Version=6.15.0
MxDb.Version=DB.6.0.150
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
OSC_IN.Mode=HSE-External-Oscillator
OSC_IN.Signal=RCC_OSC_IN
OSC_OUT.Mode=HSE-External-Oscillator
OSC_OUT.Signal=RCC_OSC_OUT
PA10.GPIOParameters=GPIO_Label
PA10.GPIO_Label=DEBUG_RX
PA10.Locked=true
PA10.Mode=Asynchronous
PA10.Signal=LPUART1_RX
PA15\ (JTDI).GPIOParameters=GPIO_Label
PA15\ (JTDI).GPIO_Label=LTE_PWRKEY
PA15\ (JTDI).Locked=true
PA15\ (JTDI).Signal=GPIO_Output
PA8.GPIOParameters=GPIO_Label
PA8.GPIO_Label=LTE_RX
PA8.Mode=Asynchronous
PA8.Signal=USART1_RX
PB0.GPIOParameters=GPIO_Label
PB0.GPIO_Label=LTE_RST
PB0.Locked=true
PB0.Signal=GPIO_Output
PB11.GPIOParameters=GPIO_Label
PB11.GPIO_Label=DEBUG_TX
PB11.Mode=Asynchronous
PB11.Signal=LPUART1_TX
PB12.GPIOParameters=GPIO_Label
PB12.GPIO_Label=LTE_TX
PB12.Mode=Asynchronous
PB12.Signal=USART1_TX
PB4\ (NJTRST).GPIOParameters=GPIO_Label
PB4\ (NJTRST).GPIO_Label=LTE_EN
PB4\ (NJTRST).Locked=true
PB4\ (NJTRST).Signal=GPIO_Output
PB7.GPIOParameters=GPIO_Label
PB7.GPIO_Label=STATUS_LED
PB7.Locked=true
PB7.Signal=GPIO_Output
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Mode=LSE-External-Oscillator
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=true
ProjectManager.CompilerLinker=GCC
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=true
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=false
ProjectManager.DeviceId=STM32WBA52CGUx
ProjectManager.FirmwarePackage=STM32Cube FW_WBA V1.7.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=2
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=WiseEye-LTE.ioc
ProjectManager.ProjectName=WiseEye-LTE
ProjectManager.ProjectStructure=
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=EWARM V9.20
ProjectManager.ToolChainLocation=
ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-SystemPower_Config-PWR-false-HAL-true,4-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-true,6-MX_ICACHE_Init-ICACHE-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true
RCC.ADCFreq_Value=64000000
RCC.AHB4Freq_Value=64000000
RCC.AHB5CLKDivider=DIV2
RCC.AHB5Freq_Value=32000000
RCC.AHBFreq_Value=64000000
RCC.APB1Freq_Value=64000000
RCC.APB1TimFreq_Value=64000000
RCC.APB2Freq_Value=64000000
RCC.APB2TimFreq_Value=64000000
RCC.APB7Freq_Value=64000000
RCC.ASFreq_Value=64000000
RCC.CortexFreq_Value=8000000
RCC.FCLKCortexFreq_Value=64000000
RCC.HCLKFreq_Value=64000000
RCC.HSESYSFreq_VALUE=32000000
RCC.HSE_VALUE=32000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=64000000
RCC.I2C3Freq_Value=64000000
RCC.IPParameters=ADCFreq_Value,AHB4Freq_Value,AHB5CLKDivider,AHB5Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB7Freq_Value,ASFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,HCLKFreq_Value,HSESYSFreq_VALUE,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,PLLFRACN,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,RNGFreq_Value,RSTFreq_Value,RSTRFFreq_Value,SAESFreq_Value,SPI1Freq_Value,SPI3Freq_Value,SYSCLKFreq_VALUE,SYSCLKSourceVirtual,USART1Freq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
RCC.LPTIM1Freq_Value=64000000
RCC.LPTIM2Freq_Value=64000000
RCC.LPUART1Freq_Value=64000000
RCC.LSCOPinFreq_Value=32000
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=64000000
RCC.PLLFRACN=0
RCC.PLLM=2
RCC.PLLN=8
RCC.PLLPoutputFreq_Value=64000000
RCC.PLLQoutputFreq_Value=64000000
RCC.PLLRCLKFreq_Value=64000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RNGFreq_Value=16000000
RCC.RSTFreq_Value=32000
RCC.RSTRFFreq_Value=32000000
RCC.SAESFreq_Value=64000000
RCC.SPI1Freq_Value=64000000
RCC.SPI3Freq_Value=64000000
RCC.SYSCLKFreq_VALUE=64000000
RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_PLLCLK
RCC.USART1Freq_Value=64000000
RCC.USART2Freq_Value=64000000
RCC.VCOInputFreq_Value=16000000
RCC.VCOOutputFreq_Value=128000000
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
VP_CORTEX_M33_NS_VS_Hclk.Mode=Hclk_Mode
VP_CORTEX_M33_NS_VS_Hclk.Signal=CORTEX_M33_NS_VS_Hclk
VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache
VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE
VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
VP_PWR_VS_SECSignals.Mode=Security/Privilege
VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom

249
WiseEye-LTE.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
CAD.formats=
CAD.pinconfig=
CAD.provider=
CORTEX_M33_NS.userName=CORTEX_M33
File.Version=6
GPIO.groupedBy=Expand Peripherals
KeepUserPlacement=false
LPUART1.BaudRate=115200
LPUART1.IPParameters=BaudRate
MMTAppReg1.MEMORYMAP.AP=RW_priv_only
MMTAppReg1.MEMORYMAP.AppRegionName=RAM
MMTAppReg1.MEMORYMAP.ContextName=CortexM33
MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M33
MMTAppReg1.MEMORYMAP.DefaultDataRegion=true
MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,AP
MMTAppReg1.MEMORYMAP.Name=RAM
MMTAppReg1.MEMORYMAP.Size=131072
MMTAppReg1.MEMORYMAP.StartAddress=0x20000000
MMTAppReg2.MEMORYMAP.AP=RO_priv_only
MMTAppReg2.MEMORYMAP.AppRegionName=FLASH
MMTAppReg2.MEMORYMAP.Cacheability=WTRA
MMTAppReg2.MEMORYMAP.ContextName=CortexM33
MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M33
MMTAppReg2.MEMORYMAP.DefaultCodeRegion=true
MMTAppReg2.MEMORYMAP.DefaultDataRegion=false
MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion
MMTAppReg2.MEMORYMAP.MemType=ROM
MMTAppReg2.MEMORYMAP.Name=FLASH
MMTAppReg2.MEMORYMAP.Size=1048576
MMTAppReg2.MEMORYMAP.StartAddress=0x08000000
MMTAppReg3.MEMORYMAP.AppRegionName=RX/TX_RAM_Radio
MMTAppReg3.MEMORYMAP.ContextName=CortexM33
MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M33
MMTAppReg3.MEMORYMAP.DefaultDataRegion=false
MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,SizeUnit,DefaultDataRegion,ContextName,Name,ReservedRegion,Security
MMTAppReg3.MEMORYMAP.Name=RX/TX_RAM_Radio
MMTAppReg3.MEMORYMAP.ReservedRegion=true
MMTAppReg3.MEMORYMAP.Security=NS
MMTAppReg3.MEMORYMAP.Size=16384
MMTAppReg3.MEMORYMAP.SizeUnit=B
MMTAppReg3.MEMORYMAP.StartAddress=0x48028000
MMTAppRegionsCount=3
MMTConfigApplied=false
Mcu.CPN=STM32WBA52CGU6
Mcu.ContextProject=TrustZoneDisabled
Mcu.Family=STM32WBA
Mcu.IP0=CORTEX_M33_NS
Mcu.IP1=DEBUG
Mcu.IP10=SYS
Mcu.IP11=USART1
Mcu.IP2=HSEM
Mcu.IP3=ICACHE
Mcu.IP4=LPUART1
Mcu.IP5=MEMORYMAP
Mcu.IP6=NVIC
Mcu.IP7=PWR
Mcu.IP8=RCC
Mcu.IP9=RTC
Mcu.IPNb=12
Mcu.Name=STM32WBA52CGUx
Mcu.Package=UFQFPN48
Mcu.Pin0=PB12
Mcu.Pin1=PB11
Mcu.Pin10=PB15
Mcu.Pin11=OSC_OUT
Mcu.Pin12=OSC_IN
Mcu.Pin13=PA10
Mcu.Pin14=VP_CORTEX_M33_NS_VS_Hclk
Mcu.Pin15=VP_HSEM_VS_HSEM
Mcu.Pin16=VP_ICACHE_VS_ICACHE
Mcu.Pin17=VP_PWR_VS_SECSignals
Mcu.Pin18=VP_RTC_VS_RTC_Activate
Mcu.Pin19=VP_RTC_VS_RTC_WakeUp_intern
Mcu.Pin2=PA8
Mcu.Pin20=VP_SYS_VS_Systick
Mcu.Pin21=VP_MEMORYMAP_VS_MEMORYMAP
Mcu.Pin3=PC15-OSC32_OUT
Mcu.Pin4=PC14-OSC32_IN
Mcu.Pin5=PB7
Mcu.Pin6=PB4 (NJTRST)
Mcu.Pin7=PA14 (JTCK/SWCLK)
Mcu.Pin8=PA13 (JTMS/SWDIO)
Mcu.Pin9=PB0
Mcu.PinsNb=22
Mcu.ThirdParty0=STMicroelectronics.X-CUBE-FREERTOS.1.3.1
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32WBA52CGUx
MxCube.Version=6.15.0
MxDb.Version=DB.6.0.150
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HSEM_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
OSC_IN.Mode=HSE-External-Oscillator
OSC_IN.Signal=RCC_OSC_IN
OSC_OUT.Mode=HSE-External-Oscillator
OSC_OUT.Signal=RCC_OSC_OUT
PA10.GPIOParameters=GPIO_Label
PA10.GPIO_Label=DEBUG_RX
PA10.Locked=true
PA10.Mode=Asynchronous
PA10.Signal=LPUART1_RX
PA13\ (JTMS/SWDIO).Mode=Serial_Wire
PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
PA14\ (JTCK/SWCLK).Mode=Serial_Wire
PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
PA8.GPIOParameters=GPIO_Label
PA8.GPIO_Label=LTE_RX
PA8.Mode=Asynchronous
PA8.Signal=USART1_RX
PB0.GPIOParameters=GPIO_Label
PB0.GPIO_Label=LTE_RST
PB0.Locked=true
PB0.Signal=GPIO_Output
PB11.GPIOParameters=GPIO_Label
PB11.GPIO_Label=DEBUG_TX
PB11.Mode=Asynchronous
PB11.Signal=LPUART1_TX
PB12.GPIOParameters=GPIO_Label
PB12.GPIO_Label=LTE_TX
PB12.Mode=Asynchronous
PB12.Signal=USART1_TX
PB15.GPIOParameters=GPIO_Label
PB15.GPIO_Label=LTE_PWRKEY
PB15.Locked=true
PB15.Signal=GPIO_Output
PB4\ (NJTRST).GPIOParameters=GPIO_Label
PB4\ (NJTRST).GPIO_Label=LTE_EN
PB4\ (NJTRST).Locked=true
PB4\ (NJTRST).Signal=GPIO_Output
PB7.GPIOParameters=GPIO_Label
PB7.GPIO_Label=STATUS_LED
PB7.Locked=true
PB7.Signal=GPIO_Output
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Mode=LSE-External-Oscillator
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=true
ProjectManager.CompilerLinker=GCC
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=true
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=false
ProjectManager.DeviceId=STM32WBA52CGUx
ProjectManager.FirmwarePackage=STM32Cube FW_WBA V1.7.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=2
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=STM32CubeIDE
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=WiseEye-LTE.ioc
ProjectManager.ProjectName=WiseEye-LTE
ProjectManager.ProjectStructure=
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=EWARM V9.20
ProjectManager.ToolChainLocation=
ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,4-SystemPower_Config-PWR-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,7-MX_ICACHE_Init-ICACHE-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_HSEM_Init-HSEM-false-HAL-true
RCC.ADCFreq_Value=64000000
RCC.AHB4Freq_Value=64000000
RCC.AHB5CLKDivider=DIV2
RCC.AHB5Freq_Value=32000000
RCC.AHBFreq_Value=64000000
RCC.APB1Freq_Value=64000000
RCC.APB1TimFreq_Value=64000000
RCC.APB2Freq_Value=64000000
RCC.APB2TimFreq_Value=64000000
RCC.APB7Freq_Value=64000000
RCC.ASFreq_Value=64000000
RCC.CortexFreq_Value=8000000
RCC.FCLKCortexFreq_Value=64000000
RCC.HCLKFreq_Value=64000000
RCC.HSESYSFreq_VALUE=32000000
RCC.HSE_VALUE=32000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=64000000
RCC.I2C3Freq_Value=64000000
RCC.IPParameters=ADCFreq_Value,AHB4Freq_Value,AHB5CLKDivider,AHB5Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB7Freq_Value,ASFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,HCLKFreq_Value,HSESYSFreq_VALUE,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,PLLFRACN,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,RNGFreq_Value,RSTFreq_Value,RSTRFFreq_Value,RTCFreq_Value,SAESFreq_Value,SPI1Freq_Value,SPI3Freq_Value,SYSCLKFreq_VALUE,SYSCLKSourceVirtual,USART1Freq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
RCC.LPTIM1Freq_Value=64000000
RCC.LPTIM2Freq_Value=64000000
RCC.LPUART1Freq_Value=64000000
RCC.LSCOPinFreq_Value=32000
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=64000000
RCC.PLLFRACN=0
RCC.PLLM=2
RCC.PLLN=8
RCC.PLLPoutputFreq_Value=64000000
RCC.PLLQoutputFreq_Value=64000000
RCC.PLLRCLKFreq_Value=64000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RNGFreq_Value=16000000
RCC.RSTFreq_Value=32000
RCC.RSTRFFreq_Value=32000000
RCC.RTCFreq_Value=32000
RCC.SAESFreq_Value=64000000
RCC.SPI1Freq_Value=64000000
RCC.SPI3Freq_Value=64000000
RCC.SYSCLKFreq_VALUE=64000000
RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_PLLCLK
RCC.USART1Freq_Value=64000000
RCC.USART2Freq_Value=64000000
RCC.VCOInputFreq_Value=16000000
RCC.VCOOutputFreq_Value=128000000
STMicroelectronics.X-CUBE-FREERTOS.1.3.1.CMSISJjRTOS2_Checked=false
STMicroelectronics.X-CUBE-FREERTOS.1.3.1_SwParameter=RTOS2CcCMSISJjRTOS2JjHeap\:HeapIi4;RTOS2CcCMSISJjRTOS2JjCore\:TZIiNonIiSupported;
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
VP_CORTEX_M33_NS_VS_Hclk.Mode=Hclk_Mode
VP_CORTEX_M33_NS_VS_Hclk.Signal=CORTEX_M33_NS_VS_Hclk
VP_HSEM_VS_HSEM.Mode=HSEM_Activate
VP_HSEM_VS_HSEM.Signal=HSEM_VS_HSEM
VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache
VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE
VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
VP_PWR_VS_SECSignals.Mode=Security/Privilege
VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_RTC_VS_RTC_WakeUp_intern.Mode=WakeUp
VP_RTC_VS_RTC_WakeUp_intern.Signal=RTC_VS_RTC_WakeUp_intern
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom